From: Xiaowei Song <songxiaowei@hisilicon.com>
To: <bhelgaas@google.com>, <kishon@ti.com>, <jingoohan1@gmail.com>,
<arnd@arndb.de>, <tn@semihalf.com>, <keith.busch@intel.com>,
<niklas.cassel@axis.com>, <dhdang@apm.com>,
<liudongdong3@huawei.com>, <gabriele.paoloni@huawei.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<catalin.marinas@arm.com>, <will.deacon@arm.com>
Cc: <chenyao11@huawei.com>, <puck.chen@hisilicon.com>,
<songxiaowei@hisilicon.com>, <guodong.xu@linaro.org>,
<wangbinghui@hisilicon.com>, <suzhuangluan@hisilicon.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v6 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
Date: Wed, 24 May 2017 16:12:45 +0800 [thread overview]
Message-ID: <20170524081248.67198-2-songxiaowei@hisilicon.com> (raw)
In-Reply-To: <20170524081248.67198-1-songxiaowei@hisilicon.com>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..ffbdcba287f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,49 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,hi3660-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpio: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ };
--
2.11.GIT
next prev parent reply other threads:[~2017-05-24 8:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-24 8:12 [PATCH v6 0/4] DT and Driver review comments fix Xiaowei Song
2017-05-24 8:12 ` Xiaowei Song [this message]
2017-05-24 8:12 ` [PATCH v6 2/4] arm64: dts: hisi: add kirin pcie node Xiaowei Song
2017-05-28 6:07 ` kbuild test robot
2017-05-24 8:12 ` [PATCH v6 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Xiaowei Song
2017-05-24 11:28 ` Jingoo Han
2017-05-24 8:12 ` [PATCH v6 4/4] defconfig: PCI: Enable Kirin PCIe defconfig Xiaowei Song
2017-05-24 11:30 ` [PATCH v6 0/4] DT and Driver review comments fix Jingoo Han
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