From: Paul Burton <paul.burton@imgtec.com>
To: <linux-pci@vger.kernel.org>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>,
Ravikiran Gummaluri <rgummal@xilinx.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Michal Simek <michal.simek@xilinx.com>,
<linux-mips@linux-mips.org>, Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH v5 3/4] PCI: xilinx: Don't enable config completion interrupts
Date: Sat, 17 Jun 2017 12:57:40 -0700 [thread overview]
Message-ID: <20170617195741.12757-4-paul.burton@imgtec.com> (raw)
In-Reply-To: <20170617195741.12757-1-paul.burton@imgtec.com>
The Xilinx AXI bridge for PCI Express device provides interrupts
indicating the completion of config space accesses. We have previously
enabled/unmasked them but do nothing with them besides acknowledge them.
Leave the interrupts masked in order to avoid servicing a large number
of pointless interrupts during boot.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
Cc: linux-pci@vger.kernel.org
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/pci/host/pcie-xilinx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 5436657d142d..176ad1608d88 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -60,6 +60,7 @@
#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
+#define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D
#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
/* Root Port Error FIFO Read Register definitions */
@@ -553,8 +554,8 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
XILINX_PCIE_IMR_ALL_MASK,
XILINX_PCIE_REG_IDR);
- /* Enable all interrupts */
- pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
+ /* Enable all interrupts we handle */
+ pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);
/* Enable the Bridge enable bit */
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
--
2.13.1
next prev parent reply other threads:[~2017-06-17 19:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-17 19:57 [PATCH v5 0/4] PCI: xilinx: Fixes, optimisation & MIPS support Paul Burton
2017-06-17 19:57 ` [PATCH v5 1/4] PCI: xilinx: Create legacy IRQ domain with size 5 Paul Burton
2017-06-19 23:47 ` Bjorn Helgaas
2017-06-20 0:38 ` Ley Foon Tan
2017-06-20 1:49 ` Bjorn Helgaas
2017-06-20 1:55 ` Ley Foon Tan
2017-06-20 2:02 ` Ley Foon Tan
2017-06-20 2:30 ` Bharat Kumar Gogada
2017-07-12 22:14 ` Bjorn Helgaas
2017-06-20 2:07 ` Paul Burton
2017-07-09 22:59 ` Paul Burton
2017-07-10 5:43 ` Bharat Kumar Gogada
2017-06-17 19:57 ` [PATCH v5 2/4] PCI: xilinx: Unify INTx & MSI interrupt decode Paul Burton
2017-06-17 19:57 ` Paul Burton [this message]
2017-06-17 19:57 ` [PATCH v5 4/4] PCI: xilinx: Allow build on MIPS platforms Paul Burton
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