From: Niklas Cassel <niklas.cassel@axis.com>
To: Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Niklas Cassel <niklass@axis.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 02/10] PCI: designware-ep: set_msi should only set MMC bits
Date: Fri, 13 Oct 2017 18:09:05 +0200 [thread overview]
Message-ID: <20171013160914.3220-3-niklas.cassel@axis.com> (raw)
In-Reply-To: <20171013160914.3220-1-niklas.cassel@axis.com>
Previously, set_msi wrote all bits in the Message Control
register, thus overwriting the 64 bit address capable bit.
By clearing the 64 bit address capable bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
drivers/pci/dwc/pcie-designware-ep.c | 4 +++-
drivers/pci/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index d53d5f168363..c92ab87fd660 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -220,7 +220,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- val = (encode_int << MSI_CAP_MMC_SHIFT);
+ val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+ val &= ~MSI_CAP_MMC_MASK;
+ val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
return 0;
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 547352a317f8..36183906e1d2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -101,6 +101,7 @@
#define MSI_MESSAGE_CONTROL 0x52
#define MSI_CAP_MMC_SHIFT 1
+#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
#define MSI_CAP_MME_SHIFT 4
#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
#define MSI_MESSAGE_ADDR_L32 0x54
--
2.11.0
next prev parent reply other threads:[~2017-10-13 16:09 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 16:09 [PATCH 00/10] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-10-13 16:09 ` [PATCH 01/10] PCI: dwc: use DMA-API for allocating MSI data Niklas Cassel
2017-10-13 16:42 ` David Laight
2017-10-16 11:43 ` Niklas Cassel
2017-10-13 16:43 ` Jingoo Han
2017-10-16 12:08 ` Niklas Cassel
2017-10-13 16:47 ` Jingoo Han
2017-10-16 12:11 ` Niklas Cassel
2017-10-16 22:16 ` Bjorn Helgaas
2017-10-13 16:09 ` Niklas Cassel [this message]
2017-10-16 22:26 ` [PATCH 02/10] PCI: designware-ep: set_msi should only set MMC bits Bjorn Helgaas
2017-10-13 16:09 ` [PATCH 03/10] PCI: designware-ep: read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-10-13 16:09 ` [PATCH 04/10] PCI: designware-ep: pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-10-13 16:09 ` [PATCH 05/10] PCI: artpec6: remove unused defines Niklas Cassel
2017-10-13 16:09 ` [PATCH 06/10] PCI: dwc: artpec6: use BIT and GENMASK macros Niklas Cassel
2017-10-13 16:09 ` [PATCH 07/10] PCI: dwc: artpec6: split artpec6_pcie_establish_link to smaller functions Niklas Cassel
2017-10-13 16:09 ` [PATCH 08/10] PCI: dwc: artpec6: add support for endpoint mode Niklas Cassel
2017-10-16 23:43 ` Bjorn Helgaas
2017-10-18 8:03 ` Kishon Vijay Abraham I
2017-10-18 8:15 ` Niklas Cassel
2017-10-18 8:47 ` Kishon Vijay Abraham I
2017-10-19 7:59 ` Christoph Hellwig
2017-10-19 10:57 ` Niklas Cassel
2017-10-19 11:40 ` Niklas Cassel
2017-10-17 22:24 ` Rob Herring
2017-10-18 8:46 ` Kishon Vijay Abraham I
2017-10-20 10:48 ` Niklas Cassel
2017-10-13 16:09 ` [PATCH 09/10] PCI: dwc: make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-10-16 12:40 ` Niklas Cassel
2017-10-13 16:09 ` [PATCH 10/10] PCI: dwc: artpec6: add support for the ARTPEC-7 SoC Niklas Cassel
2017-10-17 22:25 ` Rob Herring
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