From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lelv0142.ext.ti.com ([198.47.23.249]:43998 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388435AbeGXSil (ORCPT ); Tue, 24 Jul 2018 14:38:41 -0400 From: Vignesh R To: Tony Lindgren CC: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , , , , , Vignesh R Subject: [PATCH v3 2/4] ARM: dts: dra7: Enable workaround for errata i870 in PCIe host mode Date: Tue, 24 Jul 2018 23:01:48 +0530 Message-ID: <20180724173150.2701-3-vigneshr@ti.com> In-Reply-To: <20180724173150.2701-1-vigneshr@ti.com> References: <20180724173150.2701-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: Add ti,syscon-unaligned-access property to PCIe RC nodes to set appropriate bits in CTRL_CORE_SMA_SW_7 register to enable workaround for errata i870. Signed-off-by: Vignesh R --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a0ddf497e8cd..1050da6c6d35 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -336,6 +336,7 @@ <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; @@ -387,6 +388,7 @@ <0 0 0 2 &pcie2_intc 2>, <0 0 0 3 &pcie2_intc 3>, <0 0 0 4 &pcie2_intc 4>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; pcie2_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; -- 2.18.0