From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lelv0143.ext.ti.com ([198.47.23.248]:36538 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388435AbeGXSip (ORCPT ); Tue, 24 Jul 2018 14:38:45 -0400 From: Vignesh R To: Tony Lindgren CC: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , , , , , Vignesh R Subject: [PATCH v3 3/4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP Date: Tue, 24 Jul 2018 23:01:49 +0530 Message-ID: <20180724173150.2701-4-vigneshr@ti.com> In-Reply-To: <20180724173150.2701-1-vigneshr@ti.com> References: <20180724173150.2701-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are incorrectly documented in the TRM. In fact, the bit positions are swapped. Update the DT bindings for PCIe EP to reflect the same. Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R --- v3; Add Fixes tag arch/arm/boot/dts/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1050da6c6d35..fc50d6a8e51a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -355,7 +355,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; }; }; -- 2.18.0