From: "Woods, Brian" <Brian.Woods@amd.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
"x86@kernel.org" <x86@kernel.org>,
Clemens Ladisch <clemens@ladisch.de>,
Jean Delvare <jdelvare@suse.com>,
Guenter Roeck <linux@roeck-us.net>,
Bjorn Helgaas <bhelgaas@google.com>,
"Woods, Brian" <Brian.Woods@amd.com>, Pu Wen <puwen@hygon.cn>,
Jia Zhang <qianyue.zj@alibaba-inc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-hwmon@vger.kernel.org" <linux-hwmon@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: [PATCH v2 2/4] x86/amd_nb: add support for newer PCI topologies
Date: Tue, 6 Nov 2018 20:08:16 +0000 [thread overview]
Message-ID: <20181106200754.60722-3-brian.woods@amd.com> (raw)
In-Reply-To: <20181106200754.60722-1-brian.woods@amd.com>
Add support for new processors which have multiple PCI root complexes
per data fabric/system management network interface. If there are (N)
multiple PCI roots per DF/SMN interface, then the PCI roots are
redundant (as far as SMN/DF access goes). For each DF/SMN interface:
map to the first available PCI root and skip the next N-1 PCI roots so
the following DF/SMN interface get mapped to a correct PCI root.
Ex:
DF/SMN 0 -> 60
40
20
00
DF/SMN 1 -> e0
c0
a0
80
Signed-off-by: Brian Woods <brian.woods@amd.com>
---
arch/x86/kernel/amd_nb.c | 44 ++++++++++++++++++++++++++++++++++++++------
1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 19d489ee2b1e..cc34266e3c62 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -213,7 +213,10 @@ int amd_cache_northbridges(void)
const struct pci_device_id *root_ids = amd_root_ids;
struct pci_dev *root, *misc, *link;
struct amd_northbridge *nb;
- u16 i = 0;
+ u16 roots_per_misc = 0;
+ u16 misc_count = 0;
+ u16 root_count = 0;
+ u16 i, j;
if (amd_northbridges.num)
return 0;
@@ -226,26 +229,55 @@ int amd_cache_northbridges(void)
misc = NULL;
while ((misc = next_northbridge(misc, misc_ids)) != NULL)
- i++;
+ misc_count++;
- if (!i)
+ if (!misc_count)
return -ENODEV;
- nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
+ root = NULL;
+ while ((root = next_northbridge(root, root_ids)) != NULL)
+ root_count++;
+
+ if (root_count) {
+ roots_per_misc = root_count / misc_count;
+
+ /*
+ * There should be _exactly_ N roots for each DF/SMN
+ * interface.
+ */
+ if (!roots_per_misc || (root_count % roots_per_misc)) {
+ pr_info("Unsupported AMD DF/PCI configuration found\n");
+ return -ENODEV;
+ }
+ }
+
+ nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
if (!nb)
return -ENOMEM;
amd_northbridges.nb = nb;
- amd_northbridges.num = i;
+ amd_northbridges.num = misc_count;
link = misc = root = NULL;
- for (i = 0; i != amd_northbridges.num; i++) {
+ for (i = 0; i < amd_northbridges.num; i++) {
node_to_amd_nb(i)->root = root =
next_northbridge(root, root_ids);
node_to_amd_nb(i)->misc = misc =
next_northbridge(misc, misc_ids);
node_to_amd_nb(i)->link = link =
next_northbridge(link, link_ids);
+
+ /*
+ * If there are more PCI root devices than data fabric/
+ * system management network interfaces, then the (N)
+ * PCI roots per DF/SMN interface are functionally the
+ * same (for DF/SMN access) and N-1 are redundant. N-1
+ * PCI roots should be skipped per DF/SMN interface so
+ * the following DF/SMN interfaces get mapped to
+ * correct PCI roots.
+ */
+ for (j = 1; j < roots_per_misc; j++)
+ root = next_northbridge(root, root_ids);
}
if (amd_gart_present())
--
2.11.0
next prev parent reply other threads:[~2018-11-06 20:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-06 20:08 [PATCH v2 0/4] Update DF/SMN access and k10temp for AMD F17h M30h Woods, Brian
2018-11-06 20:08 ` [PATCH v2 1/4] k10temp: x86/amd_nb: consolidate shared device IDs Woods, Brian
2018-11-06 22:45 ` Guenter Roeck
2018-11-07 20:42 ` [tip:x86/amd-nb] hwmon/k10temp, x86/amd_nb: Consolidate " tip-bot for Woods, Brian
2018-11-06 20:08 ` Woods, Brian [this message]
2018-11-07 20:43 ` [tip:x86/amd-nb] x86/amd_nb: Add support for newer PCI topologies tip-bot for Woods, Brian
2018-11-06 20:08 ` [PATCH v2 3/4] x86/amd_nb: add PCI device IDs for F17h M30h Woods, Brian
2018-11-07 20:44 ` [tip:x86/amd-nb] x86/amd_nb: Add PCI device IDs for family 17h, model 30h tip-bot for Woods, Brian
2018-11-06 20:08 ` [PATCH v2 4/4] hwmon: k10temp: add support for AMD F17h M30h CPUs Woods, Brian
2018-11-06 22:45 ` Guenter Roeck
2018-11-07 20:44 ` [tip:x86/amd-nb] hwmon/k10temp: Add support for AMD family 17h, model 30h CPUs tip-bot for Woods, Brian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181106200754.60722-3-brian.woods@amd.com \
--to=brian.woods@amd.com \
--cc=bhelgaas@google.com \
--cc=bp@alien8.de \
--cc=clemens@ladisch.de \
--cc=hpa@zytor.com \
--cc=jdelvare@suse.com \
--cc=linux-hwmon@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux@roeck-us.net \
--cc=mingo@redhat.com \
--cc=puwen@hygon.cn \
--cc=qianyue.zj@alibaba-inc.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).