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[5.150.229.118]) by smtp.gmail.com with ESMTPSA id i78sm2728954lfa.9.2018.12.03.10.02.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 10:02:10 -0800 (PST) Date: Mon, 3 Dec 2018 19:02:08 +0100 From: Niklas Cassel To: Marc Zyngier Cc: linux-pci@vger.kernel.org, Lorenzo Pieralisi , Bjorn Helgaas , Trent Piepho , Jingoo Han , Gustavo Pimentel , faiz_abbas@ti.com, Joao Pinto , Vignesh R Subject: Re: [1/3] PCI: designware: Use interrupt masking instead of disabling Message-ID: <20181203180208.GA18985@centauri.lan> References: <20181113225734.8026-2-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181113225734.8026-2-marc.zyngier@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Nov 13, 2018 at 10:57:32PM +0000, Marc Zyngier wrote: > The dwc driver is showing an interesting level of brokeness, as it > insists on using the "enable" register to mask/unmask MSIs, meaning > that an MSIs being generated while the interrupt is in that "disabled" > state will simply be lost. > > Let's move to the MASK register, which offers the expected semantics. > > Signed-off-by: Marc Zyngier > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 29a05759a294..c3aa8b5fb51d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -168,7 +168,7 @@ static void dw_pci_bottom_mask(struct irq_data *data) > bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; > > pp->irq_status[ctrl] &= ~(1 << bit); > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, > pp->irq_status[ctrl]); > } > > @@ -191,7 +191,7 @@ static void dw_pci_bottom_unmask(struct irq_data *data) > bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; > > pp->irq_status[ctrl] |= 1 << bit; > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, > pp->irq_status[ctrl]); > } > For this patch combined with the fix-up from: https://marc.info/?l=linux-pci&m=154218928401960&w=2 Tested-by: Niklas Cassel