From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
Leo Li <leoyang.li@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
"Z.q. Hou" <zhiqiang.hou@nxp.com>
Subject: [PATCHv3 3/5] PCI: dwc: fix potential memory leak
Date: Tue, 18 Dec 2018 04:19:37 +0000 [thread overview]
Message-ID: <20181218041956.41809-4-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20181218041956.41809-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To avoid memory leak on error return of the adjacent function
devm_of_pci_get_host_bridge_resources(), change to use
devm_pci_alloc_host_bridge() to allocate host bridge structure,
then it will be managed automatically.
Fixes: 295aeb98a322 ("PCI: designware: Convert PCI scan API to
pci_scan_root_bus_bridge()")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- Changed to use devm_* to allocate host bridge.
- Added Fixes info.
.../pci/controller/dwc/pcie-designware-host.c | 28 ++++++++-----------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 29a05759a294..33b5a3815d24 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -346,7 +346,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(dev, "Missing *config* reg space\n");
}
- bridge = pci_alloc_host_bridge(0);
+ bridge = devm_pci_alloc_host_bridge(dev, 0);
if (!bridge)
return -ENOMEM;
@@ -357,7 +357,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
ret = devm_request_pci_bus_resources(dev, &bridge->windows);
if (ret)
- goto error;
+ return ret;
/* Get the I/O and memory ranges from DT */
resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
@@ -401,8 +401,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
resource_size(pp->cfg));
if (!pci->dbi_base) {
dev_err(dev, "Error with ioremap\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -413,8 +412,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg0_base, pp->cfg0_size);
if (!pp->va_cfg0_base) {
dev_err(dev, "Error with ioremap in function\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -424,8 +422,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg1_size);
if (!pp->va_cfg1_base) {
dev_err(dev, "Error with ioremap\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -448,14 +445,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->num_vectors == 0) {
dev_err(dev,
"Invalid number of vectors\n");
- goto error;
+ return -EINVAL;
}
}
if (!pp->ops->msi_host_init) {
ret = dw_pcie_allocate_domains(pp);
if (ret)
- goto error;
+ return ret;
if (pp->msi_irq)
irq_set_chained_handler_and_data(pp->msi_irq,
@@ -464,14 +461,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
} else {
ret = pp->ops->msi_host_init(pp);
if (ret < 0)
- goto error;
+ return ret;
}
}
if (pp->ops->host_init) {
ret = pp->ops->host_init(pp);
if (ret)
- goto error;
+ return ret;
}
pp->root_bus_nr = pp->busn->start;
@@ -485,7 +482,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
ret = pci_scan_root_bus_bridge(bridge);
if (ret)
- goto error;
+ return ret;
bus = bridge->bus;
@@ -499,11 +496,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
- return 0;
-error:
- pci_free_host_bridge(bridge);
- return ret;
+ return 0;
}
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
--
2.17.1
next prev parent reply other threads:[~2018-12-18 4:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 4:19 [PATCHv3 0/5] PCI: dwc: add prefetchable memory range support Z.q. Hou
2018-12-18 4:19 ` [PATCHv3 1/5] ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes Z.q. Hou
2019-01-11 7:30 ` Shawn Guo
2018-12-18 4:19 ` [PATCHv3 2/5] arm64: dts: layerscape: " Z.q. Hou
2019-01-11 7:30 ` Shawn Guo
2018-12-18 4:19 ` Z.q. Hou [this message]
2018-12-18 4:19 ` [PATCHv3 4/5] PCI: dwc: fix 4GiB outbound window size truncated to zero issue Z.q. Hou
2018-12-18 4:19 ` [PATCHv3 5/5] PCI: dwc: add prefetchable memory range support Z.q. Hou
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