Re: [PATCH v2] PCI: Block power management of certain ports with slot implemented bit set

[Mika Westerberg <mika.westerberg@linux.intel.com>]

On Mon, Jan 07, 2019 at 02:13:14PM +0100, Rafael J. Wysocki wrote:
> On Mon, Jan 7, 2019 at 2:01 PM Mika Westerberg
> <mika.westerberg@linux.intel.com> wrote:
> >
> > Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is
> > connected to Alpine Ridge Thunderbolt controller. This port has slot
> > implemented bit set in the config space but other than that it is not
> > hotplug capable in the sense we are expecting in Linux (it has
> > dev->is_hotplug_bridge set to 0):
> >
> > 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5
> >         Bus: primary=00, secondary=05, subordinate=46, sec-latency=0
> >         Memory behind bridge: 78000000-8fffffff [size=384M]
> >         Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M]
> >         ...
> >         Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
> >         ...
> >                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
> >                         Slot #8, PowerLimit 25.000W; Interlock- NoCompl+
> >                 SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> >                         Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> >                 SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
> >                         Changed: MRL- PresDet+ LinkState+
> >
> > This system is using ACPI based hotplug to notify the OS that it needs
> > to rescan the PCI bus (ACPI hotplug).
> >
> > If there is nothing connected to any of the Thunderbolt ports the root
> > port will not have any runtime PM active children and is thus
> > automatically runtime suspended pretty soon after boot by PCI PM core.
> > Now, when a device is connected the BIOS SMI handler responsible for
> > enumerating newly added devices is not able to find anything because the
> > port is in D3.
> >
> > For this reason we block power management of PCIe root and downstream
> > ports that have slot implemented set and have node in ACPI namespace.
> >
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=202031
> > Reported-by: Kedar A Dongre <kedar.a.dongre@intel.com>
> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> 
> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

Thanks!

However, I'm having second toughts about this because I remembered that
people put a lot of effort getting discrete graphics with power resource
attached to the root port powering off properly. If the root port
matches the criteria in this patch it will not be able to go into D3
anymore. It might affect others such as M.2 connected NVMe or WiFi chip
as well. For that reason I would still prefer blacklist, at least for now.