Hello Luis,

Sorry for the long delay, the Christmas/New Year vacation and some
personal issues got in the way.

On Tue, 18 Dec 2018 23:13:59 +0000, Luís Mendes wrote:

> The complete lspci outputs follow in attachments.
> 
> In the working case, region 5, is at e0200000 with size 256k and is
> immediately followed by the expansion rom at  e0240000 [disabled]
> [size=128K], however in the non-working case,
> region 5 has a completely different address, and regions are not contiguous.
> Another difference is at:
> Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
>         Address: 00000000f1020a04  Data: 0f12
> 
> vs
> 
>     Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
>         Address: 0000000000000000  Data: 0000
> 
> So it looks like MSI is not being enabled with the new PCI management
> code and looks like the PCI rom maybe mapped to an invalid memory
> address, causing the ioremap to fail.

Could you apply the patches attached (one is meant to be used with 4.20
as-is, and the other meant to be used with 4.20 +
1f08673eef1236f7d02d93fcf596bb8531ef0d12 reverted), and post the
complete boot logs ?

You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
having dropped messages, as my additional debug messages are quite
verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.

Having these boot lots will help me investigate the issue.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com