Fwd: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space

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* Fwd: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
       [not found] ` <CAEzXK1po4ik1oHdwVvVMWEqh8KMdAMY7sxv9OR2bYs54qV6EyA@mail.gmail.com>
@ 2018-12-18 13:42   ` Luís Mendes
  0 siblings, 0 replies; 13+ messages in thread
From: Luís Mendes @ 2018-12-18 13:42 UTC (permalink / raw)
  To: Thomas Petazzoni, Lorenzo Pieralisi, Linux PCI

[-- Attachment #1: Type: text/plain, Size: 583 bytes --]

Retrying email again, because, message was rejected by linux-pci
mailing list, due to not being a plain-text. Sorry for the
inconvenience.

Hi Thomas, Lorenzo,

I've been running Linux on a armhf with an AMD gpu card and since this
commit, in linux 4.20, the amdgpu driver causes a kernel oops and
fails to initialize when calling pci_map_rom, which then fails on a
call to ioremap_page_range. If I revert the patch from commit

1f08673eef1236f7d02d93fcf596bb8531ef0d12
 then amdgpu successfully initializes.

The kernel oops follows in attachment.

Regards,
Luís

[-- Attachment #2: PCI_problem_4.20-rc4.txt --]
[-- Type: text/plain, Size: 9683 bytes --]

[   10.133435] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf14e0000
[   10.141118] pgd = (ptrval)
[   10.143836] [f14e0000] *pgd=2c4ff811, *pte=e0200243, *ppte=e0200013
[   10.150126] Internal error: : 1008 [#1] SMP ARM
[   10.154665] Modules linked in: si2168 rfkill amdgpu(+) snd_rawmidi snd_seq snd_seq_device snd_timer chash gpu_sched ttm drm_kms_helper smipcie(+) snd drm syscopyarea sysfillrect sysimgblt fb_sys_fops soundcore binfmt_misc sch_fq_codel ip_tables x_tables autofs4
[   10.177856] CPU: 1 PID: 259 Comm: systemd-udevd Not tainted 4.20.0-rc4-next3g-clearfog #1
[   10.186051] Hardware name: Marvell Armada 380/385 (Device Tree)
[   10.191989] PC is at pci_map_rom+0x88/0x1f4
[   10.196181] LR is at ioremap_page_range+0x10c/0x1b8
[   10.201069] pc : [<c07bb520>]    lr : [<c0bdb61c>]    psr: a0070113
[   10.207348] sp : ec0a5a58  ip : eed20000  fp : ec0a5a7c
[   10.212583] r10: ec551000  r9 : bf3bf6dc  r8 : 00020000
[   10.217818] r7 : ec0a5a80  r6 : ee2a1800  r5 : f14e0000  r4 : f14e0000
[   10.224359] r3 : 00000012  r2 : 0000aa55  r1 : 52494350  r0 : f1500000
[   10.230901] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
[   10.238052] Control: 10c5387d  Table: 2c0a804a  DAC: 00000051
[   10.243809] Process systemd-udevd (pid: 259, stack limit = 0x(ptrval))
[   10.250350] Stack: (0xec0a5a58 to 0xec0a6000)
[   10.254715] 5a40:                                                       ec550000 ec550000
[   10.262913] 5a60: c1005dc8 00000100 00000009 bf3bf6dc ec0a5aa4 ec0a5a80 bf1b5d8c c07bb4a4
[   10.271109] 5a80: 00020000 6ab4ddaf c1005dc8 ec550000 ec552000 00000100 ec0a5b0c ec0a5aa8
[   10.279304] 5aa0: bf1b5e9c bf1b5d58 c1005dc8 ec556000 ec558000 00000100 ec0a5ae4 ec0a5ac8
[   10.287500] 5ac0: c01bc074 c01bc75c ec0a5aec 6ab4ddaf bf216aa8 c0875474 ec0a5b0c ec0a5ae8
[   10.295697] 5ae0: c0875474 c0bf5b18 ec550000 6ab4ddaf ec552000 ec550000 ec558000 ec552000
[   10.303893] 5b00: ec0a5ba4 ec0a5b10 bf196c6c bf1b5e38 00000000 0000e367 000000ff c0bf1a9c
[   10.312089] 5b20: ec33e420 00000000 00000000 6ab4ddaf ec0a5b64 c02d72a8 ec552000 bf387d00
[   10.320286] 5b40: bf3ba258 c1005dc8 00000004 ec33f640 ec0a5b6c ec0a5b60 c02d72a8 c02e121c
[   10.328483] 5b60: ec0a5ba4 ec0a5b70 c02d72e0 c02d7280 ec33f640 6ab4ddaf ec33f640 ec05b800
[   10.336680] 5b80: ec550000 00000010 bf3ba000 00000000 ec33f640 00000000 ec0a5bc4 ec0a5ba8
[   10.344877] 5ba0: bf19aab0 bf1961e4 ec05b800 00000000 00000010 bf3ba000 ec0a5bfc ec0a5bc8
[   10.353074] 5bc0: bf06cba8 bf19aa2c 00080001 6ab4ddaf 00000000 ee2a1800 00000000 ee2a1800
[   10.361271] 5be0: bf337440 ec05b800 bf387488 bf337440 ec0a5c24 ec0a5c00 bf1943e0 bf06ca7c
[   10.369468] 5c00: ee2a1878 ee2a1800 bf3ba0f0 00000000 bf3ba128 bf337440 ec0a5c4c ec0a5c28
[   10.377665] 5c20: c07b8c90 bf194320 c114e02c ee2a1878 c114e030 00000000 bf3ba128 0000000c
[   10.385862] 5c40: ec0a5c84 ec0a5c50 c08801c8 c07b8be8 00000000 c1005dc8 ec0a5c84 ee2a1878
[   10.394059] 5c60: bf3ba128 bf3ba128 c1005dc8 ec3fa2a4 c1005dc8 ec0a5f38 ec0a5cbc ec0a5c88
[   10.402255] 5c80: c0880628 c087ff04 c0bf0bd8 c01cda40 ee2a18ac ee2a18ac ee2a1878 ee2a18ac
[   10.410452] 5ca0: bf3ba128 c1005dc8 ec3fa2a4 c1005dc8 ec0a5cdc ec0a5cc0 c088075c c0880488
[   10.418648] 5cc0: 00000000 bf3ba128 c0880650 c1005dc8 ec0a5d0c ec0a5ce0 c087db50 c088065c
[   10.426845] 5ce0: ee1c916c ee1c9158 ed1c5d34 6ab4ddaf bf3ba128 c109d050 ec009a00 00000000
[   10.435042] 5d00: ec0a5d1c ec0a5d10 c087f93c c087dad8 ec0a5d44 ec0a5d20 c087f1f4 c087f91c
[   10.443238] 5d20: bf3874f0 ec0a5d30 bf3ba128 bf3874f0 ec3fa280 00000000 ec0a5d5c ec0a5d48
[   10.451435] 5d40: c08814c4 c087f098 00000000 bf3874f0 ec0a5d74 ec0a5d60 c07b6d54 c0881444
[   10.459631] 5d60: bf3bf6c0 bf404000 ec0a5d8c ec0a5d78 bf40407c c07b6d08 c1005dc8 bf404000
[   10.467828] 5d80: ec0a5e04 ec0a5d90 c01033ac bf40400c c02cd258 6ab4ddaf 00000001 c0bf0bd8
[   10.476025] 5da0: 00000000 006000c0 ec0a5dcc ec0a5db8 c0bf0bd8 c01cda40 006000c0 c030d3f0
[   10.484220] 5dc0: ec0a5e04 ec0a5dd0 c030d3f0 c02d88c0 00000001 0000032b ed783440 6ab4ddaf
[   10.492417] 5de0: 00000001 bf3bf4c0 00000001 ec3fa280 ec3f8440 ec3fa2a4 ec0a5e2c ec0a5e08
[   10.500614] 5e00: c01fa6e4 c0103368 ec0a5e2c ec0a5e18 00000001 00000001 ec3fa280 c01f5aa0
[   10.508811] 5e20: ec0a5f14 ec0a5e30 c01f96b4 c01fa67c bf3bf4cc 00007fff bf3bf4c0 c01f6800
[   10.517008] 5e40: c1005dc8 c0d90194 c0d901a8 c0d90188 c0d901d0 c0e5abd0 bf3bf5f0 bf3bf5d4
[   10.525205] 5e60: bf3bf4c4 bf3bf6a0 c0c070a4 c01f5b68 bf3bf508 bf3bf4c0 00000000 c0e8a0cc
[   10.533403] 5e80: ec0a5f30 0032aab0 ec0a5ee4 ec0a5e98 00000000 00000000 00000000 00000000
[   10.541599] 5ea0: 00000000 00000000 6e72656b 00006c65 00000000 00000000 00000000 00000000
[   10.549796] 5ec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[   10.557992] 5ee0: 00000000 6ab4ddaf 7fffffff c1005dc8 00000000 00000017 b6db61bc c0101204
[   10.566189] 5f00: ec0a4000 0000017b ec0a5fa4 ec0a5f18 c01f9eec c01f736c 7fffffff 00000000
[   10.574386] 5f20: 00000003 ec0a5f24 ec0a5f24 f0eb0000 0032aab0 00000000 f10a8a35 f10e8a40
[   10.582583] 5f40: f0eb0000 0032aab0 f11da218 f11da018 f112ab88 00233000 0024df60 bf3bba70
[   10.590778] 5f60: 00000191 00000000 0006e5d0 00000034 00000035 0000002b 00000019 0000000c
[   10.598975] 5f80: 00000000 6ab4ddaf 0066fb68 becbb9a4 99e26e00 0000017b 00000000 ec0a5fa8
[   10.607172] 5fa0: c01011e4 c01f9e38 0066fb68 becbb9a4 00000017 b6db61bc 00000000 006715c0
[   10.615369] 5fc0: 0066fb68 becbb9a4 99e26e00 0000017b 00685340 becbb99c 00000000 00680450
[   10.623566] 5fe0: becbb898 becbb888 b6db0951 b6e5ef42 400f0030 00000017 00000000 00000000
[   10.631760] Backtrace: 
[   10.634669] [<c07bb498>] (pci_map_rom) from [<bf1b5d8c>] (amdgpu_read_bios+0x40/0xe0 [amdgpu])
[   10.643303]  r9:bf3bf6dc r8:00000009 r7:00000100 r6:c1005dc8 r5:ec550000 r4:ec550000
[   10.651710] [<bf1b5d4c>] (amdgpu_read_bios [amdgpu]) from [<bf1b5e9c>] (amdgpu_get_bios+0x70/0x228 [amdgpu])
[   10.661561]  r7:00000100 r6:ec552000 r5:ec550000 r4:c1005dc8
[   10.667827] [<bf1b5e2c>] (amdgpu_get_bios [amdgpu]) from [<bf196c6c>] (amdgpu_device_init+0xa94/0x1724 [amdgpu])
[   10.678025]  r6:ec552000 r5:ec558000 r4:ec550000
[   10.683241] [<bf1961d8>] (amdgpu_device_init [amdgpu]) from [<bf19aab0>] (amdgpu_driver_load_kms+0x90/0x254 [amdgpu])
[   10.693876]  r10:00000000 r9:ec33f640 r8:00000000 r7:bf3ba000 r6:00000010 r5:ec550000
[   10.701721]  r4:ec05b800
[   10.704589] [<bf19aa20>] (amdgpu_driver_load_kms [amdgpu]) from [<bf06cba8>] (drm_dev_register+0x138/0x1d8 [drm])
[   10.714874]  r7:bf3ba000 r6:00000010 r5:00000000 r4:ec05b800
[   10.720872] [<bf06ca70>] (drm_dev_register [drm]) from [<bf1943e0>] (amdgpu_pci_probe+0xcc/0x148 [amdgpu])
[   10.730549]  r9:bf337440 r8:bf387488 r7:ec05b800 r6:bf337440 r5:ee2a1800 r4:00000000
[   10.738610] [<bf194314>] (amdgpu_pci_probe [amdgpu]) from [<c07b8c90>] (pci_device_probe+0xb4/0x148)
[   10.747765]  r9:bf337440 r8:bf3ba128 r7:00000000 r6:bf3ba0f0 r5:ee2a1800 r4:ee2a1878
[   10.755530] [<c07b8bdc>] (pci_device_probe) from [<c08801c8>] (really_probe+0x2d0/0x3f0)
[   10.763639]  r9:0000000c r8:bf3ba128 r7:00000000 r6:c114e030 r5:ee2a1878 r4:c114e02c
[   10.771402] [<c087fef8>] (really_probe) from [<c0880628>] (driver_probe_device+0x1ac/0x1d4)
[   10.779772]  r10:ec0a5f38 r9:c1005dc8 r8:ec3fa2a4 r7:c1005dc8 r6:bf3ba128 r5:bf3ba128
[   10.787618]  r4:ee2a1878
[   10.790157] [<c088047c>] (driver_probe_device) from [<c088075c>] (__driver_attach+0x10c/0x134)
[   10.798789]  r9:c1005dc8 r8:ec3fa2a4 r7:c1005dc8 r6:bf3ba128 r5:ee2a18ac r4:ee2a1878
[   10.806551] [<c0880650>] (__driver_attach) from [<c087db50>] (bus_for_each_dev+0x84/0xc4)
[   10.814747]  r7:c1005dc8 r6:c0880650 r5:bf3ba128 r4:00000000
[   10.820420] [<c087dacc>] (bus_for_each_dev) from [<c087f93c>] (driver_attach+0x2c/0x30)
[   10.828441]  r7:00000000 r6:ec009a00 r5:c109d050 r4:bf3ba128
[   10.834115] [<c087f910>] (driver_attach) from [<c087f1f4>] (bus_add_driver+0x168/0x268)
[   10.842138] [<c087f08c>] (bus_add_driver) from [<c08814c4>] (driver_register+0x8c/0x124)
[   10.850246]  r7:00000000 r6:ec3fa280 r5:bf3874f0 r4:bf3ba128
[   10.855918] [<c0881438>] (driver_register) from [<c07b6d54>] (__pci_register_driver+0x58/0x5c)
[   10.864547]  r5:bf3874f0 r4:00000000
[   10.868439] [<c07b6cfc>] (__pci_register_driver) from [<bf40407c>] (amdgpu_init+0x7c/0x90 [amdgpu])
[   10.877505]  r5:bf404000 r4:bf3bf6c0
[   10.881394] [<bf404000>] (amdgpu_init [amdgpu]) from [<c01033ac>] (do_one_initcall+0x50/0x210)
[   10.890024]  r5:bf404000 r4:c1005dc8
[   10.893610] [<c010335c>] (do_one_initcall) from [<c01fa6e4>] (do_init_module+0x74/0x224)
[   10.901719]  r8:ec3fa2a4 r7:ec3f8440 r6:ec3fa280 r5:00000001 r4:bf3bf4c0
[   10.908437] [<c01fa670>] (do_init_module) from [<c01f96b4>] (load_module+0x2354/0x28dc)
[   10.916458]  r7:c01f5aa0 r6:ec3fa280 r5:00000001 r4:00000001
[   10.922131] [<c01f7360>] (load_module) from [<c01f9eec>] (sys_finit_module+0xc0/0x110)
[   10.930067]  r10:0000017b r9:ec0a4000 r8:c0101204 r7:b6db61bc r6:00000017 r5:00000000
[   10.937912]  r4:c1005dc8
[   10.940451] [<c01f9e2c>] (sys_finit_module) from [<c01011e4>] (__sys_trace_return+0x0/0x1c)
[   10.948819] Exception stack(0xec0a5fa8 to 0xec0a5ff0)
[   10.953882] 5fa0:                   0066fb68 becbb9a4 00000017 b6db61bc 00000000 006715c0
[   10.962079] 5fc0: 0066fb68 becbb9a4 99e26e00 0000017b 00685340 becbb99c 00000000 00680450
[   10.970275] 5fe0: becbb898 becbb888 b6db0951 b6e5ef42
[   10.975336]  r7:0000017b r6:99e26e00 r5:becbb9a4 r4:0066fb68
[   10.981010] Code: e3451249 e1a04005 e30a2a55 e0850008 (e1d430b0) 
[   10.987118] ---[ end trace 79bebd9e706704aa ]---


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
       [not found] <CAEzXK1o9L-bVRGBpAo+a_wYqXZh6_zuebF221Bd8=b-DTL1Q9g@mail.gmail.com>
       [not found] ` <CAEzXK1po4ik1oHdwVvVMWEqh8KMdAMY7sxv9OR2bYs54qV6EyA@mail.gmail.com>
@ 2018-12-18 13:47 ` Thomas Petazzoni
  2018-12-18 14:34   ` Thomas Petazzoni
  1 sibling, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2018-12-18 13:47 UTC (permalink / raw)
  To: Luís Mendes; +Cc: linux-pci, Lorenzo Pieralisi

Hello,

On Tue, 18 Dec 2018 12:31:51 +0000, Luís Mendes wrote:

> I've been running Linux on a armhf with an AMD gpu card and since this
> commit, in linux 4.20, the amdgpu driver causes a kernel oops and fails to
> initialize when calling pci_map_rom, which then fails on a call to
> ioremap_page_range. If I revert the patch from commit
> 
> 1f08673eef1236f7d02d93fcf596bb8531ef0d12
> <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v4.20-rc7&id=1f08673eef1236f7d02d93fcf596bb8531ef0d12>
> then
> amdgpu successfully initializes.
> 
> The kernel oops follows in attachment.

Thanks for the bug report! I have an idea of what could be causing
this, I've cooked a patch, I'm doing a build test. I of course won't be
able to test it as I don't have amdgpu hardware, but I'll share the
patch with you for testing.

Note: I'm not sure where you found <linux-pci@atrey.karlin.mff.cuni.cz>
to be the address of the linux-pci mailing list, it's really
linux-pci@vger.kernel.org.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2018-12-18 13:47 ` Thomas Petazzoni
@ 2018-12-18 14:34   ` Thomas Petazzoni
  2018-12-18 15:42     ` Luís Mendes
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2018-12-18 14:34 UTC (permalink / raw)
  To: Luís Mendes; +Cc: linux-pci, Lorenzo Pieralisi

Hello Luis,

On Tue, 18 Dec 2018 14:47:02 +0100, Thomas Petazzoni wrote:

> Thanks for the bug report! I have an idea of what could be causing
> this, I've cooked a patch, I'm doing a build test. I of course won't be
> able to test it as I don't have amdgpu hardware, but I'll share the
> patch with you for testing.

Could you try the below patch:

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index fa0fc46edb0c..62468415e063 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -469,6 +469,23 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
        return PCI_BRIDGE_EMUL_HANDLED;
 }
 
+static pci_bridge_emul_read_status_t
+mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
+                                    int reg, u32 *value)
+{
+       switch(reg) {
+       case PCI_ROM_ADDRESS1:
+               /* We don't support the PCI ROM mechanism */
+               *value = 0;
+               break;
+
+       default:
+               return PCI_BRIDGE_EMUL_NOT_HANDLED;
+       }
+
+       return PCI_BRIDGE_EMUL_HANDLED;
+}
+
 static void
 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
                                      int reg, u32 old, u32 new, u32 mask)
@@ -555,6 +572,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
 }
 
 struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
+       .read_base = mvebu_pci_bridge_emul_base_conf_read,
        .write_base = mvebu_pci_bridge_emul_base_conf_write,
        .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
        .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,

If that fixes the problem for you, I'll send it as a proper patch with
a commit log that explains the issue.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2018-12-18 14:34   ` Thomas Petazzoni
@ 2018-12-18 15:42     ` Luís Mendes
  2018-12-18 20:37       ` Thomas Petazzoni
  0 siblings, 1 reply; 13+ messages in thread
From: Luís Mendes @ 2018-12-18 15:42 UTC (permalink / raw)
  To: Thomas Petazzoni; +Cc: Linux PCI, Lorenzo Pieralisi

Hi Thomas,

Thanks a lot for your quick reply and patch, but unfortunately the
problem remains the same with the patch applied.

How can I help to further pin down the issue?

Regards,
Luís

---
Luís Mendes, Researcher, Instituto Superior Técnico
Hardware and Software engineer
http://tecnico.ulisboa.pt/

On Tue, Dec 18, 2018 at 2:34 PM Thomas Petazzoni
<thomas.petazzoni@bootlin.com> wrote:
>
> Hello Luis,
>
> On Tue, 18 Dec 2018 14:47:02 +0100, Thomas Petazzoni wrote:
>
> > Thanks for the bug report! I have an idea of what could be causing
> > this, I've cooked a patch, I'm doing a build test. I of course won't be
> > able to test it as I don't have amdgpu hardware, but I'll share the
> > patch with you for testing.
>
> Could you try the below patch:
>
> diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> index fa0fc46edb0c..62468415e063 100644
> --- a/drivers/pci/controller/pci-mvebu.c
> +++ b/drivers/pci/controller/pci-mvebu.c
> @@ -469,6 +469,23 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
>         return PCI_BRIDGE_EMUL_HANDLED;
>  }
>
> +static pci_bridge_emul_read_status_t
> +mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
> +                                    int reg, u32 *value)
> +{
> +       switch(reg) {
> +       case PCI_ROM_ADDRESS1:
> +               /* We don't support the PCI ROM mechanism */
> +               *value = 0;
> +               break;
> +
> +       default:
> +               return PCI_BRIDGE_EMUL_NOT_HANDLED;
> +       }
> +
> +       return PCI_BRIDGE_EMUL_HANDLED;
> +}
> +
>  static void
>  mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
>                                       int reg, u32 old, u32 new, u32 mask)
> @@ -555,6 +572,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
>  }
>
>  struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
> +       .read_base = mvebu_pci_bridge_emul_base_conf_read,
>         .write_base = mvebu_pci_bridge_emul_base_conf_write,
>         .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
>         .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
>
> If that fixes the problem for you, I'll send it as a proper patch with
> a commit log that explains the issue.
>
> Thanks,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2018-12-18 15:42     ` Luís Mendes
@ 2018-12-18 20:37       ` Thomas Petazzoni
  2018-12-18 23:13         ` Luís Mendes
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2018-12-18 20:37 UTC (permalink / raw)
  To: Luís Mendes; +Cc: Linux PCI, Lorenzo Pieralisi

Hello,

On Tue, 18 Dec 2018 15:42:34 +0000, Luís Mendes wrote:

> Thanks a lot for your quick reply and patch, but unfortunately the
> problem remains the same with the patch applied.

Gaah, too bad. A shot in the dark sometimes works, sometimes not.

> How can I help to further pin down the issue?

Could you post the output of:

lspci -vvv -xxx

with the "PCI: mvebu: Convert to PCI emulated bridge config space"
patch applied and reverted, and send the result ? This would allow me
to look at the differences in the configuration space exposed by the
emulated bridge and hopefully see which one might cause the regression.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2018-12-18 20:37       ` Thomas Petazzoni
@ 2018-12-18 23:13         ` Luís Mendes
  2019-01-08 10:48           ` Thomas Petazzoni
  0 siblings, 1 reply; 13+ messages in thread
From: Luís Mendes @ 2018-12-18 23:13 UTC (permalink / raw)
  To: Thomas Petazzoni; +Cc: Linux PCI, Lorenzo Pieralisi

[-- Attachment #1: Type: text/plain, Size: 1796 bytes --]

Hello again,

The complete lspci outputs follow in attachments.

In the working case, region 5, is at e0200000 with size 256k and is
immediately followed by the expansion rom at  e0240000 [disabled]
[size=128K], however in the non-working case,
region 5 has a completely different address, and regions are not contiguous.
Another difference is at:
Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
        Address: 00000000f1020a04  Data: 0f12

vs

    Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
        Address: 0000000000000000  Data: 0000

So it looks like MSI is not being enabled with the new PCI management
code and looks like the PCI rom maybe mapped to an invalid memory
address, causing the ioremap to fail.

Regards,
Luís Mendes, Researcher, Instituto Superior Técnico
Hardware and Software engineer
https://tecnico.ulisboa.pt/en/

On Tue, Dec 18, 2018 at 8:37 PM Thomas Petazzoni
<thomas.petazzoni@bootlin.com> wrote:
>
> Hello,
>
> On Tue, 18 Dec 2018 15:42:34 +0000, Luís Mendes wrote:
>
> > Thanks a lot for your quick reply and patch, but unfortunately the
> > problem remains the same with the patch applied.
>
> Gaah, too bad. A shot in the dark sometimes works, sometimes not.
>
> > How can I help to further pin down the issue?
>
> Could you post the output of:
>
> lspci -vvv -xxx
>
> with the "PCI: mvebu: Convert to PCI emulated bridge config space"
> patch applied and reverted, and send the result ? This would allow me
> to look at the differences in the configuration space exposed by the
> emulated bridge and hopefully see which one might cause the regression.
>
> Thanks,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

[-- Attachment #2: lspci_with_commit.txt --]
[-- Type: text/plain, Size: 17506 bytes --]

$ sudo lspci -vvv -xxx
00:01.0 PCI bridge: Marvell Technology Group Ltd. Device 6828 (rev 0a) (prog-if 00 [Normal decode])
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: e8000000-e80fffff
	Prefetchable memory behind bridge: fff00000-000fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort+ >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Kernel driver in use: pcieport
00: ab 11 28 68 46 01 10 00 0a 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f1 01 00 00
20: 00 e8 00 e8 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 21 00
40: 10 00 42 01 80 80 00 00 00 20 00 00 12 ac 03 00
50: 40 00 11 10 00 00 00 00 00 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.0 PCI bridge: Marvell Technology Group Ltd. Device 6828 (rev 0a) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00010000-00010fff
	Memory behind bridge: e8100000-e81fffff
	Prefetchable memory behind bridge: d0000000-e7ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort+ >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Kernel driver in use: pcieport
00: ab 11 28 68 47 01 10 00 0a 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 01 01 00 00
20: 10 e8 10 e8 00 d0 f0 e7 00 00 00 00 00 00 00 00
30: 01 00 01 00 40 00 00 00 00 00 00 00 00 00 21 00
40: 10 00 42 01 80 80 00 00 00 20 01 00 12 ac 03 00
50: 40 00 12 10 00 00 00 00 00 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 Multimedia video controller: Spin Master Ltd. PCIe Video Bridge (rev 01)
	Subsystem: DVBSky PCIe Video Bridge
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 48
	Region 0: Memory at e8000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
		Address: 00000000f1020a04  Data: 0f10
	Capabilities: [70] Express (v1) Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 128 bytes Disabled- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Kernel driver in use: SMI PCIe driver
	Kernel modules: smipcie
00: de 1a 38 30 06 04 10 00 01 00 00 04 00 00 00 00
10: 00 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 54 42 80 55
30: 00 00 00 00 40 00 00 00 00 00 00 00 2f 01 00 00
40: 01 50 03 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 89 00 04 0a 02 f1 00 00 00 00 10 0f 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 00 01 00 01 80 00 00 10 20 00 00 11 f4 03 00
80: 08 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Baffin [Polaris11] (rev ff) (prog-if 00 [VGA controller])
	Subsystem: Sapphire Technology Limited Baffin [Radeon RX 560]
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 49
	Region 0: Memory at d0000000 (64-bit, prefetchable) [size=256M]
	Region 2: Memory at e0000000 (64-bit, prefetchable) [size=2M]
	Region 4: I/O ports at 10000 [size=256]
	Region 5: Memory at e8100000 (32-bit, non-prefetchable) [size=256K]
	Expansion ROM at e0200000 [size=128K]
	Capabilities: [48] Vendor Specific Information: Len=08 <?>
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <64ns, L1 <1us
			ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
		LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
	Capabilities: [150 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [200 v1] #15
	Capabilities: [270 v1] #19
	Capabilities: [2b0 v1] Address Translation Service (ATS)
		ATSCap:	Invalidate Queue Depth: 00
		ATSCtl:	Enable-, Smallest Translation Unit: 00
	Capabilities: [2c0 v1] Page Request Interface (PRI)
		PRICtl: Enable- Reset-
		PRISta: RF- UPRGI- Stopped+
		Page Request Capacity: 00000020, Page Request Allocation: 00000000
	Capabilities: [2d0 v1] Process Address Space ID (PASID)
		PASIDCap: Exec+ Priv+, Max PASID Width: 10
		PASIDCtl: Enable- Exec- Priv-
	Capabilities: [320 v1] Latency Tolerance Reporting
		Max snoop latency: 0ns
		Max no snoop latency: 0ns
	Capabilities: [328 v1] Alternative Routing-ID Interpretation (ARI)
		ARICap:	MFVC- ACS-, Next Function: 1
		ARICtl:	MFVC- ACS-, Function Group: 0
	Capabilities: [370 v1] L1 PM Substates
		L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
			  PortCommonModeRestoreTime=0us PortTPowerOnTime=170us
		L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
			   T_CommonMode=0us LTR1.2_Threshold=0ns
		L1SubCtl2: T_PwrOn=10us
	Kernel driver in use: amdgpu
	Kernel modules: amdgpu
00: 02 10 ff 67 43 01 10 00 ff 00 00 03 10 00 80 00
10: 0c 00 00 d0 00 00 00 00 0c 00 00 e0 00 00 00 00
20: 01 00 01 00 00 00 10 e8 00 00 00 00 a2 1d 67 e3
30: 01 00 20 e0 48 00 00 00 00 00 00 00 31 01 00 00
40: 00 00 00 00 00 00 00 00 09 50 08 00 a2 1d 67 e3
50: 01 58 03 f6 08 00 00 00 10 a0 12 00 a1 8f 00 00
60: 10 29 09 00 83 08 44 00 40 00 12 10 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 80 09 70 00
80: 00 00 00 00 0e 00 00 00 03 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device aae0
	Subsystem: Sapphire Technology Limited Device aae0
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin B routed to IRQ 50
	Region 0: Memory at e8140000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: [48] Vendor Specific Information: Len=08 <?>
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <64ns, L1 <1us
			ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 00000000f1020a04  Data: 0f11
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
	Capabilities: [150 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [328 v1] Alternative Routing-ID Interpretation (ARI)
		ARICap:	MFVC- ACS-, Next Function: 0
		ARICtl:	MFVC- ACS-, Function Group: 0
	Kernel driver in use: snd_hda_intel
	Kernel modules: snd_hda_intel
00: 02 10 e0 aa 46 05 10 00 00 00 03 04 10 00 80 00
10: 04 00 14 e8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 a2 1d e0 aa
30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 02 00 00
40: 00 00 00 00 00 00 00 00 09 50 08 00 a2 1d e0 aa
50: 01 58 03 06 08 00 00 00 10 a0 12 00 a1 8f 00 00
60: 10 29 09 00 83 08 44 00 40 00 12 10 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 80 09 70 00
80: 00 00 00 00 0e 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 00 81 00 04 0a 02 f1 00 00 00 00 11 0f 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

[-- Attachment #3: lspci_with_commit_reverted.txt --]
[-- Type: text/plain, Size: 17557 bytes --]

$ sudo lspci -vvv -xxx
00:01.0 PCI bridge: Marvell Technology Group Ltd. Device 6828 (rev 0a) (prog-if 00 [Normal decode])
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: e8000000-e80fffff
	Prefetchable memory behind bridge: 00000000-000fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Kernel driver in use: pcieport
00: ab 11 28 68 46 01 10 00 0a 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f1 01 00 00
20: 00 e8 00 e8 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 10 00 42 01 80 80 00 00 00 20 00 00 12 ac 03 00
50: 40 00 11 10 00 00 00 00 00 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.0 PCI bridge: Marvell Technology Group Ltd. Device 6828 (rev 0a) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00010000-00010fff
	Memory behind bridge: d0000000-e7ffffff
	Prefetchable memory behind bridge: 00000000-000fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Kernel driver in use: pcieport
00: ab 11 28 68 47 01 10 00 0a 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 01 01 00 00
20: 00 d0 f0 e7 00 00 00 00 00 00 00 00 00 00 00 00
30: 01 00 01 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 10 00 42 01 80 80 00 00 00 20 01 00 12 ac 03 00
50: 40 00 12 10 00 00 00 00 00 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 Multimedia video controller: Spin Master Ltd. PCIe Video Bridge (rev 01)
	Subsystem: DVBSky PCIe Video Bridge
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 48
	Region 0: Memory at e8000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [50] MSI: Enable+ Count=1/16 Maskable- 64bit+
		Address: 00000000f1020a04  Data: 0f10
	Capabilities: [70] Express (v1) Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 128 bytes Disabled- CommClk-
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Kernel driver in use: SMI PCIe driver
	Kernel modules: smipcie
00: de 1a 38 30 06 04 10 00 01 00 00 04 00 00 00 00
10: 00 00 00 e8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 54 42 80 55
30: 00 00 00 00 40 00 00 00 00 00 00 00 2f 01 00 00
40: 01 50 03 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 89 00 04 0a 02 f1 00 00 00 00 10 0f 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 00 01 00 01 80 00 00 10 20 00 00 11 f4 03 00
80: 08 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Baffin [Polaris11] (rev ff) (prog-if 00 [VGA controller])
	Subsystem: Sapphire Technology Limited Baffin [Radeon RX 560]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 51
	Region 0: Memory at d0000000 (64-bit, prefetchable) [size=256M]
	Region 2: Memory at e0000000 (64-bit, prefetchable) [size=2M]
	Region 4: I/O ports at 10000 [size=256]
	Region 5: Memory at e0200000 (32-bit, non-prefetchable) [size=256K]
	Expansion ROM at e0240000 [disabled] [size=128K]
	Capabilities: [48] Vendor Specific Information: Len=08 <?>
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <64ns, L1 <1us
			ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
		LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 00000000f1020a04  Data: 0f12
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
	Capabilities: [150 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [200 v1] #15
	Capabilities: [270 v1] #19
	Capabilities: [2b0 v1] Address Translation Service (ATS)
		ATSCap:	Invalidate Queue Depth: 00
		ATSCtl:	Enable-, Smallest Translation Unit: 00
	Capabilities: [2c0 v1] Page Request Interface (PRI)
		PRICtl: Enable- Reset-
		PRISta: RF- UPRGI- Stopped+
		Page Request Capacity: 00000020, Page Request Allocation: 00000000
	Capabilities: [2d0 v1] Process Address Space ID (PASID)
		PASIDCap: Exec+ Priv+, Max PASID Width: 10
		PASIDCtl: Enable- Exec- Priv-
	Capabilities: [320 v1] Latency Tolerance Reporting
		Max snoop latency: 0ns
		Max no snoop latency: 0ns
	Capabilities: [328 v1] Alternative Routing-ID Interpretation (ARI)
		ARICap:	MFVC- ACS-, Next Function: 1
		ARICtl:	MFVC- ACS-, Function Group: 0
	Capabilities: [370 v1] L1 PM Substates
		L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
			  PortCommonModeRestoreTime=0us PortTPowerOnTime=170us
		L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
			   T_CommonMode=0us LTR1.2_Threshold=0ns
		L1SubCtl2: T_PwrOn=10us
	Kernel driver in use: amdgpu
	Kernel modules: amdgpu
00: 02 10 ff 67 47 05 10 00 ff 00 00 03 10 00 80 00
10: 0c 00 00 d0 00 00 00 00 0c 00 00 e0 00 00 00 00
20: 01 00 01 00 00 00 20 e0 00 00 00 00 a2 1d 67 e3
30: 00 00 24 e0 48 00 00 00 00 00 00 00 31 01 00 00
40: 00 00 00 00 00 00 00 00 09 50 08 00 a2 1d 67 e3
50: 01 58 03 f6 08 00 00 00 10 a0 12 00 a1 8f 00 00
60: 10 29 09 00 83 08 44 00 40 00 12 10 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 80 09 70 00
80: 00 00 00 00 0e 00 00 00 03 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 00 81 00 04 0a 02 f1 00 00 00 00 12 0f 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device aae0
	Subsystem: Sapphire Technology Limited Device aae0
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin B routed to IRQ 50
	Region 0: Memory at e0260000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: [48] Vendor Specific Information: Len=08 <?>
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
			ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <64ns, L1 <1us
			ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Not Supported
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
		Address: 00000000f1020a04  Data: 0f11
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
	Capabilities: [150 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
	Capabilities: [328 v1] Alternative Routing-ID Interpretation (ARI)
		ARICap:	MFVC- ACS-, Next Function: 0
		ARICtl:	MFVC- ACS-, Function Group: 0
	Kernel driver in use: snd_hda_intel
	Kernel modules: snd_hda_intel
00: 02 10 e0 aa 46 05 10 00 00 00 03 04 10 00 80 00
10: 04 00 26 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 a2 1d e0 aa
30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 02 00 00
40: 00 00 00 00 00 00 00 00 09 50 08 00 a2 1d e0 aa
50: 01 58 03 06 08 00 00 00 10 a0 12 00 a1 8f 00 00
60: 10 29 09 00 83 08 44 00 40 00 12 10 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 80 09 70 00
80: 00 00 00 00 0e 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 00 81 00 04 0a 02 f1 00 00 00 00 11 0f 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2018-12-18 23:13         ` Luís Mendes
@ 2019-01-08 10:48           ` Thomas Petazzoni
       [not found]             ` <CAEzXK1oQd1YNZ5pyNXA76h-3CbBRxmTke=Z-SRusyfqL=Wd8eA@mail.gmail.com>
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2019-01-08 10:48 UTC (permalink / raw)
  To: Luís Mendes; +Cc: Linux PCI, Lorenzo Pieralisi

[-- Attachment #1: Type: text/plain, Size: 1543 bytes --]

Hello Luis,

Sorry for the long delay, the Christmas/New Year vacation and some
personal issues got in the way.

On Tue, 18 Dec 2018 23:13:59 +0000, Luís Mendes wrote:

> The complete lspci outputs follow in attachments.
> 
> In the working case, region 5, is at e0200000 with size 256k and is
> immediately followed by the expansion rom at  e0240000 [disabled]
> [size=128K], however in the non-working case,
> region 5 has a completely different address, and regions are not contiguous.
> Another difference is at:
> Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
>         Address: 00000000f1020a04  Data: 0f12
> 
> vs
> 
>     Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
>         Address: 0000000000000000  Data: 0000
> 
> So it looks like MSI is not being enabled with the new PCI management
> code and looks like the PCI rom maybe mapped to an invalid memory
> address, causing the ioremap to fail.

Could you apply the patches attached (one is meant to be used with 4.20
as-is, and the other meant to be used with 4.20 +
1f08673eef1236f7d02d93fcf596bb8531ef0d12 reverted), and post the
complete boot logs ?

You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
having dropped messages, as my additional debug messages are quite
verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.

Having these boot lots will help me investigate the issue.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #2: 0001-PCI-mvebu-add-debug.patch --]
[-- Type: text/x-patch, Size: 2011 bytes --]

From 2bd51f2891150b524f73e58c55da5fe68a7d1457 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Date: Tue, 8 Jan 2019 10:59:19 +0100
Subject: [PATCH] PCI: mvebu: add debug

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
 drivers/pci/controller/pci-mvebu.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index fa0fc46edb0c..9715ba070263 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -624,9 +624,13 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
+	if (bus->number == 0) {
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, val);
 		return pci_bridge_emul_conf_write(&port->bridge, where,
 						  size, val);
+	}
 
 	if (!mvebu_pcie_link_up(port))
 		return PCIBIOS_DEVICE_NOT_FOUND;
@@ -653,9 +657,14 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 	}
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
-		return pci_bridge_emul_conf_read(&port->bridge, where,
-						 size, val);
+	if (bus->number == 0) {
+		ret = pci_bridge_emul_conf_read(&port->bridge, where,
+						size, val);
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, *val);
+		return ret;
+	}
 
 	if (!mvebu_pcie_link_up(port)) {
 		*val = 0xffffffff;
@@ -986,6 +995,8 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 	/* Get the PCIe IO aperture */
 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
 
+	dev_info(dev, "MEM: %pR, IO: %pR\n", &pcie->mem, &pcie->io);
+
 	if (resource_size(&pcie->io) != 0) {
 		pcie->realio.flags = pcie->io.flags;
 		pcie->realio.start = PCIBIOS_MIN_IO;
-- 
2.20.1


[-- Attachment #3: 0001-PCI-mvebu-add-debug-after-revert.patch --]
[-- Type: text/x-patch, Size: 1957 bytes --]

From ac0aa231c23390150dddfdf923400af2a4a4e86b Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Date: Tue, 8 Jan 2019 10:59:19 +0100
Subject: [PATCH] PCI: mvebu: add debug

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
 drivers/pci/controller/pci-mvebu.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index dacad51f19e7..94aa7e42c5e2 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -796,8 +796,12 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
+	if (bus->number == 0) {
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, val);
 		return mvebu_sw_pci_bridge_write(port, where, size, val);
+	}
 
 	if (!mvebu_pcie_link_up(port))
 		return PCIBIOS_DEVICE_NOT_FOUND;
@@ -824,8 +828,13 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 	}
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
-		return mvebu_sw_pci_bridge_read(port, where, size, val);
+	if (bus->number == 0) {
+		ret = mvebu_sw_pci_bridge_read(port, where, size, val);
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, *val);
+		return ret;
+	}
 
 	if (!mvebu_pcie_link_up(port)) {
 		*val = 0xffffffff;
@@ -1156,6 +1165,8 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 	/* Get the PCIe IO aperture */
 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
 
+	dev_info(dev, "MEM: %pR, IO: %pR\n", &pcie->mem, &pcie->io);
+
 	if (resource_size(&pcie->io) != 0) {
 		pcie->realio.flags = pcie->io.flags;
 		pcie->realio.start = PCIBIOS_MIN_IO;
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

[parent not found: <CAEzXK1oQd1YNZ5pyNXA76h-3CbBRxmTke=Z-SRusyfqL=Wd8eA@mail.gmail.com>]

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
       [not found]             ` <CAEzXK1oQd1YNZ5pyNXA76h-3CbBRxmTke=Z-SRusyfqL=Wd8eA@mail.gmail.com>
@ 2019-01-09  8:15               ` Thomas Petazzoni
       [not found]                 ` <CAEzXK1oHqOb3pojfX7JqrirxjOFj=UZZfi6tNNO4y6yC3u9LAA@mail.gmail.com>
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2019-01-09  8:15 UTC (permalink / raw)
  To: Luís Mendes; +Cc: Linux PCI, Lorenzo Pieralisi

Hello Luis,

On Tue, 8 Jan 2019 23:22:05 +0000, Luís Mendes wrote:

> > Sorry for the long delay, the Christmas/New Year vacation and some
> > personal issues got in the way.  
> No problem, life has its priorities! and by the way: Happy new year!

Thanks, you too!


> > You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
> > having dropped messages, as my additional debug messages are quite
> > verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.  
> The logs from the new kernel are not starting at 0.0 sec, as
> CONFIG_LOG_BUF_SHIFT=16 wasn't large enough, but for the reverted
> patch case I changed to CONFIG_LOG_BUF_SHIFT=17.
> If you find relevant information can be missing tell me and I will
> recompile the kernel with the patch
> 1f08673eef1236f7d02d93fcf596bb8531ef0d12 applied and
> CONFIG_LOG_BUF_SHIFT=17. I believe it won't be needed though, since
> the pci logs are practically complete.

Sadly, the kern_4.20_debug.log file is incomplete. I would like to at
least see it starting from:

Jan  8 22:57:51 picolo kernel: [    6.792819] mvebu-pcie soc:pcie: MEM: [mem 0xd0000000-0xefffffff], IO: [io  0xffe00000-0xffefffff]

(this line from the reverted log, but I'd like to see it in the non-reverted log as well)

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

[parent not found: <CAEzXK1oHqOb3pojfX7JqrirxjOFj=UZZfi6tNNO4y6yC3u9LAA@mail.gmail.com>]

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
       [not found]                 ` <CAEzXK1oHqOb3pojfX7JqrirxjOFj=UZZfi6tNNO4y6yC3u9LAA@mail.gmail.com>
@ 2019-02-04 11:09                   ` Luís Mendes
  2019-02-12 13:41                     ` Thomas Petazzoni
  0 siblings, 1 reply; 13+ messages in thread
From: Luís Mendes @ 2019-02-04 11:09 UTC (permalink / raw)
  To: Thomas Petazzoni; +Cc: Linux PCI, Lorenzo Pieralisi

Hi Thomas,

Have you been able to find the issue from the logs?

Best regards,
Luís Mendes

On Wed, Jan 9, 2019 at 2:38 PM Luís Mendes <luis.p.mendes@gmail.com> wrote:
>
> Hello Thomas,
>
> Replies in between.
>
> Best regards,
> Luís
>
>
> On Wed, Jan 9, 2019 at 8:15 AM Thomas Petazzoni
> <thomas.petazzoni@bootlin.com> wrote:
> >
> > Hello Luis,
> >
> > On Tue, 8 Jan 2019 23:22:05 +0000, Luís Mendes wrote:
> >
> > > > Sorry for the long delay, the Christmas/New Year vacation and some
> > > > personal issues got in the way.
> > > No problem, life has its priorities! and by the way: Happy new year!
> >
> > Thanks, you too!
>
> Thanks!
>
> >
> >
> > > > You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
> > > > having dropped messages, as my additional debug messages are quite
> > > > verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.
> > > The logs from the new kernel are not starting at 0.0 sec, as
> > > CONFIG_LOG_BUF_SHIFT=16 wasn't large enough, but for the reverted
> > > patch case I changed to CONFIG_LOG_BUF_SHIFT=17.
> > > If you find relevant information can be missing tell me and I will
> > > recompile the kernel with the patch
> > > 1f08673eef1236f7d02d93fcf596bb8531ef0d12 applied and
> > > CONFIG_LOG_BUF_SHIFT=17. I believe it won't be needed though, since
> > > the pci logs are practically complete.
> >
> > Sadly, the kern_4.20_debug.log file is incomplete. I would like to at
> > least see it starting from:
> >
> > Jan  8 22:57:51 picolo kernel: [    6.792819] mvebu-pcie soc:pcie: MEM: [mem 0xd0000000-0xefffffff], IO: [io  0xffe00000-0xffefffff]
> >
> > (this line from the reverted log, but I'd like to see it in the non-reverted log as well)
>
> In attachment follows the requested complete log using CONFIG_LOG_BUF_SHIFT=17.
>
> >
> > Thanks!
> >
> > Thomas
> > --
> > Thomas Petazzoni, CTO, Bootlin
> > Embedded Linux and Kernel engineering
> > https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2019-02-04 11:09                   ` Luís Mendes
@ 2019-02-12 13:41                     ` Thomas Petazzoni
  2019-02-13 11:34                       ` Luís Mendes
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2019-02-12 13:41 UTC (permalink / raw)
  To: Luís Mendes; +Cc: Linux PCI, Lorenzo Pieralisi

Hello,

On Mon, 4 Feb 2019 11:09:23 +0000
Luís Mendes <luis.p.mendes@gmail.com> wrote:

> Have you been able to find the issue from the logs?

A separate issue was found with the pci-mvebu integration with the new
emulated bridge code, I added you in the thread.

Could you test if:

  https://github.com/tpetazzoni/linux/tree/5.0/marvell/pci-mvebu-fix

improves the situation for you ?

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2019-02-12 13:41                     ` Thomas Petazzoni
@ 2019-02-13 11:34                       ` Luís Mendes
  2019-02-13 12:33                         ` Thomas Petazzoni
  0 siblings, 1 reply; 13+ messages in thread
From: Luís Mendes @ 2019-02-13 11:34 UTC (permalink / raw)
  To: Thomas Petazzoni; +Cc: Linux PCI, Lorenzo Pieralisi

Hello Thomas,

The kernel with pci-mvebu-fix you provided is working nicely with the
AMD graphics card, and other PCI cards that I've tested including an
Intel I350.

If you want you can add a:
Tested-by: Luis Mendes <luis.p.mendes@gmail.com>

Luis

On Tue, Feb 12, 2019 at 1:41 PM Thomas Petazzoni
<thomas.petazzoni@bootlin.com> wrote:
>
> Hello,
>
> On Mon, 4 Feb 2019 11:09:23 +0000
> Luís Mendes <luis.p.mendes@gmail.com> wrote:
>
> > Have you been able to find the issue from the logs?
>
> A separate issue was found with the pci-mvebu integration with the new
> emulated bridge code, I added you in the thread.
>
> Could you test if:
>
>   https://github.com/tpetazzoni/linux/tree/5.0/marvell/pci-mvebu-fix
>
> improves the situation for you ?
>
> Thanks!
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2019-02-13 11:34                       ` Luís Mendes
@ 2019-02-13 12:33                         ` Thomas Petazzoni
  2019-02-13 13:24                           ` Luís Mendes
  0 siblings, 1 reply; 13+ messages in thread
From: Thomas Petazzoni @ 2019-02-13 12:33 UTC (permalink / raw)
  To: Luís Mendes; +Cc: Linux PCI, Lorenzo Pieralisi

Hello Luis,

On Wed, 13 Feb 2019 11:34:36 +0000
Luís Mendes <luis.p.mendes@gmail.com> wrote:

> The kernel with pci-mvebu-fix you provided is working nicely with the
> AMD graphics card, and other PCI cards that I've tested including an
> Intel I350.
> 
> If you want you can add a:
> Tested-by: Luis Mendes <luis.p.mendes@gmail.com>

Thanks a lot, glad to hear that it fixes the problem. I will submit
those patches, and see what the feedback is.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space
  2019-02-13 12:33                         ` Thomas Petazzoni
@ 2019-02-13 13:24                           ` Luís Mendes
  0 siblings, 0 replies; 13+ messages in thread
From: Luís Mendes @ 2019-02-13 13:24 UTC (permalink / raw)
  To: Thomas Petazzoni; +Cc: Linux PCI, Lorenzo Pieralisi

Ok, great!! Thank you too, for sorting this out.

On Wed, Feb 13, 2019 at 12:33 PM Thomas Petazzoni
<thomas.petazzoni@bootlin.com> wrote:
>
> Hello Luis,
>
> On Wed, 13 Feb 2019 11:34:36 +0000
> Luís Mendes <luis.p.mendes@gmail.com> wrote:
>
> > The kernel with pci-mvebu-fix you provided is working nicely with the
> > AMD graphics card, and other PCI cards that I've tested including an
> > Intel I350.
> >
> > If you want you can add a:
> > Tested-by: Luis Mendes <luis.p.mendes@gmail.com>
>
> Thanks a lot, glad to hear that it fixes the problem. I will submit
> those patches, and see what the feedback is.
>
> Thanks!
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2019-02-13 13:24 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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2018-12-18 13:42   ` Fwd: Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space Luís Mendes
2018-12-18 13:47 ` Thomas Petazzoni
2018-12-18 14:34   ` Thomas Petazzoni
2018-12-18 15:42     ` Luís Mendes
2018-12-18 20:37       ` Thomas Petazzoni
2018-12-18 23:13         ` Luís Mendes
2019-01-08 10:48           ` Thomas Petazzoni
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2019-01-09  8:15               ` Thomas Petazzoni
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2019-02-04 11:09                   ` Luís Mendes
2019-02-12 13:41                     ` Thomas Petazzoni
2019-02-13 11:34                       ` Luís Mendes
2019-02-13 12:33                         ` Thomas Petazzoni
2019-02-13 13:24                           ` Luís Mendes

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