From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Peter Wu <peter@lekensteyn.nl>
Cc: Lukas Wunner <lukas@wunner.de>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kedar A Dongre <kedar.a.dongre@intel.com>,
Linux PCI <linux-pci@vger.kernel.org>,
ACPI Devel Maling List <linux-acpi@vger.kernel.org>
Subject: Re: [PATCH v2] PCI: Block power management of certain ports with slot implemented bit set
Date: Tue, 8 Jan 2019 14:45:59 +0200 [thread overview]
Message-ID: <20190108124559.GZ2469@lahna.fi.intel.com> (raw)
In-Reply-To: <20190108105824.GC23218@al>
On Tue, Jan 08, 2019 at 11:58:24AM +0100, Peter Wu wrote:
> > Would this patch:
> >
> > https://patchwork.ozlabs.org/patch/1021317/
> >
> > break runtime D3cold for the discrete GPU on Optimus laptops such as
> > your Clevo P651RA? Specifically, is the Root Port above the GPU
> > marked "(Slot+)" in lspci -vv? (There doesn't seem to be raw lspci
> > output in https://github.com/Lekensteyn/acpi-stuff)
>
> Thanks for bringing this into my attention. There are a couple of full
> lspci dumps, for example for the Dell XPS 9560.
> https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/lspci-bare-metal.txt
> This has upstream port 00:01.0 attached to GPU 01:00.0
>
> 00:01.0 PCI bridge [0604]: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor PCIe Controller (x16) [8086:1901] (rev 05) (prog-if 00 [Normal decode])
> ...
> Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00
>
> and would indeed be negatively affected by this patch. I can observe the
> same for the Clevo P651RA (for which I can also send the full lspci dump
> if you need).
Thanks both.
I guess that leaves us the blacklist. I can re-send it rebased on top of
v5.0-rc1 if there are no objections.
next prev parent reply other threads:[~2019-01-08 12:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-07 13:01 [PATCH v2] PCI: Block power management of certain ports with slot implemented bit set Mika Westerberg
2019-01-07 13:13 ` Rafael J. Wysocki
2019-01-08 9:35 ` Mika Westerberg
2019-01-08 9:43 ` Rafael J. Wysocki
2019-01-08 10:16 ` Lukas Wunner
2019-01-08 10:58 ` Peter Wu
2019-01-08 12:45 ` Mika Westerberg [this message]
2019-01-08 21:00 ` Lukas Wunner
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