From: Bjorn Helgaas <helgaas@kernel.org>
To: "Stefan Mätje" <stefan.maetje@esd.eu>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH 1/1] PCI/ASPM: Add a fix for an erratum of the PI7C9X111SLB PCI-to-PCIe bridge
Date: Wed, 30 Jan 2019 17:26:05 -0600 [thread overview]
Message-ID: <20190130232605.GN229773@google.com> (raw)
In-Reply-To: <20181101192229.48352-2-stefan.maetje@esd.eu>
Hi Stefan,
On Thu, Nov 01, 2018 at 08:22:29PM +0100, Stefan Mätje wrote:
> Due to an erratum in the Pericom PI7C9X111SLB bridge in reverse mode the
> retrain link bit needs to be cleared again manually to allow the link
> training to succeed.
>
> If it is not cleared manually the link training is continuously restarted
> and all devices below the PCI-to-PCIe bridge can't be accessed any more.
> That means drivers for devices below the bridge will be loaded but won't
> work or even crash because the driver is only reading 0xffff.
>
> See also the Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
Is there a public URL for this?
Are there any bug reports for which you could include URLs?
> Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
> ---
> drivers/pci/pcie/aspm.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 5326916715d2..89a245023aa9 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -268,6 +268,15 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
> /* Retrain link */
> reg16 |= PCI_EXP_LNKCTL_RL;
> pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
> + if (0x12d8 == parent->vendor && 0xe111 == parent->device) {
> + /*
> + * Due to an erratum in the Pericom PI7C9X111SLB bridge in
> + * reverse mode the retrain link bit needs to be cleared
> + * again manually to allow the link training to succeed.
> + */
> + reg16 &= ~PCI_EXP_LNKCTL_RL;
> + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
There's no timing constraint, e.g., PCI_EXP_LNKCTL_RL doesn't have to be
maintained for some minimum time before being cleared?
> + }
Sinan suggested a quirk, which I think is a good idea. Possible
implementation:
- add a pcie_retrain_link() interface (internal to PCI core, maybe even
internal to aspm.c)
- call pcie_retrain_link() from pcie_aspm_configure_common_clock()
- add a pci_dev.clear_retrain_link:1 bit
- set the bit in a quirk
- test the bit in pcie_retrain_link()
> /* Wait for link training end. Break out after waiting for timeout */
> start_jiffies = jiffies;
> --
> 2.15.0
>
next prev parent reply other threads:[~2019-01-30 23:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 19:22 [PATCH 0/1] PCI/ASPM: Proposal to add a fix for an erratum of the PI7C9X111SLB PCI-to-PCIe bridge Stefan Mätje
2018-11-01 19:22 ` [PATCH 1/1] PCI/ASPM: Add " Stefan Mätje
2018-11-01 20:06 ` Sinan Kaya
2018-11-02 11:08 ` Stefan Mätje
2019-01-30 23:26 ` Bjorn Helgaas [this message]
2019-02-07 15:16 ` Stefan Mätje
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