Re: [PATCH v4] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports

From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kedar A Dongre <kedar.a.dongre@intel.com>,
	Lukas Wunner <lukas@wunner.de>, Peter Wu <peter@lekensteyn.nl>,
	linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v4] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports
Date: Mon, 11 Feb 2019 12:27:12 +0200	[thread overview]
Message-ID: <20190211102712.GX7875@lahna.fi.intel.com> (raw)
In-Reply-To: <20190208002731.GS7268@google.com>

Hi,

On Thu, Feb 07, 2019 at 06:27:31PM -0600, Bjorn Helgaas wrote:
> On Thu, Jan 31, 2019 at 07:38:56PM +0300, Mika Westerberg wrote:
> > Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is
> > connected to an Alpine Ridge Thunderbolt controller. This port has slot
> > implemented bit set in the config space but other than that it is not
> > hotplug capable in the sense we are expecting in Linux (it has
> > dev->is_hotplug_bridge set to 0):
> > 
> > 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5
> >         Bus: primary=00, secondary=05, subordinate=46, sec-latency=0
> >         Memory behind bridge: 78000000-8fffffff [size=384M]
> >         Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M]
> >         ...
> >         Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
> >         ...
> >                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
> >                         Slot #8, PowerLimit 25.000W; Interlock- NoCompl+
> >                 SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> >                         Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> >                 SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
> >                         Changed: MRL- PresDet+ LinkState+
> > 
> > This system is using ACPI based hotplug to notify the OS that it needs
> > to rescan the PCI bus (ACPI hotplug).
> > 
> > If there is nothing connected in any of the Thunderbolt ports the root
> > port will not have any runtime PM active children and is thus
> > automatically runtime suspended pretty soon after boot by PCI PM core.
> > Now, when a device is connected the BIOS SMI handler responsible for
> > enumerating newly added devices is not able to find anything because the
> > port is in D3.
> > 
> > Prevent this from happening by blacklisting PCI power management of this
> > particular Gigabyte system.
> 
> Since this is one of those issues we seem to have to discover
> experimentally, I'd like to include a URL here to a kernel.org
> bugzilla that has a dmesg log, "lspci -vvvnn" output, an acpidump, and
> anything else that might be useful to extend or generalize this in the
> future.  Maybe dmidecode output, too?
> 
> If somebody creates the bugzilla, I can add the URL; no need to repost
> just for that.

Here it is:

https://bugzilla.kernel.org/show_bug.cgi?id=202031