[PATCH v1 0/2] PCI/ASPM: Fix LTR issues

[PATCH v1 0/2] PCI/ASPM: Fix LTR issues

[Bjorn Helgaas]

These are to fix a couple LTR-related issues found while investigating
https://bugzilla.kernel.org/show_bug.cgi?id=201469

I don't claim that these fix the whole problem of that bugzilla, but I
think it's pretty clear that these are problems we need to fix, so I want
to give these a little more exposure.

Feedback welcome!

---

Bjorn Helgaas (2):
      PCI/ASPM: Use LTR if already enabled by platform
      PCI/ASPM: Save LTR Capability for suspend/resume


 drivers/pci/pci.c   |   53 +++++++++++++++++++++++++++++++++++++++++++++++++--
 drivers/pci/probe.c |   36 ++++++++++++++++++++++-------------
 2 files changed, 74 insertions(+), 15 deletions(-)

[PATCH v1 1/2] PCI/ASPM: Use LTR if already enabled by platform

[Bjorn Helgaas]

From: Bjorn Helgaas <bhelgaas@google.com>

RussianNeuroMancer reported that the Intel 7265 wifi on a Dell Venue 11 Pro
7140 table stopped working after wakeup from suspend and bisected the
problem to 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't
have LTR").  David Ward reported the same problem on a Dell Latitude 7350.

After af8bb9f89838 ("PCI/ACPI: Request LTR control from platform before
using it"), we don't enable LTR unless the platform has granted LTR control
to us.  In addition, we don't notice if the platform had already enabled
LTR itself.

After 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't have
LTR"), we avoid using LTR if we don't think the path to the device has LTR
enabled.

The combination means that if the platform itself enables LTR but declines
to give the OS control over LTR, we unnecessarily avoided using ASPM L1.2.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=201469
Fixes: 9ab105deb60f ("PCI/ASPM: Disable ASPM L1.2 Substate if we don't have LTR")
Fixes: af8bb9f89838 ("PCI/ACPI: Request LTR control from platform before using it")
Reported-by: RussianNeuroMancer <russianneuromancer@ya.ru>
Reported-by: David Ward <david.ward@ll.mit.edu>
CC: stable@vger.kernel.org	# v4.18+
---
 drivers/pci/probe.c |   36 +++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 257b9f6f2ebb..c46a3fcb341e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2071,11 +2071,8 @@ static void pci_configure_ltr(struct pci_dev *dev)
 {
 #ifdef CONFIG_PCIEASPM
 	struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
-	u32 cap;
 	struct pci_dev *bridge;
-
-	if (!host->native_ltr)
-		return;
+	u32 cap, ctl;
 
 	if (!pci_is_pcie(dev))
 		return;
@@ -2084,22 +2081,35 @@ static void pci_configure_ltr(struct pci_dev *dev)
 	if (!(cap & PCI_EXP_DEVCAP2_LTR))
 		return;
 
-	/*
-	 * Software must not enable LTR in an Endpoint unless the Root
-	 * Complex and all intermediate Switches indicate support for LTR.
-	 * PCIe r3.1, sec 6.18.
-	 */
-	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
-		dev->ltr_path = 1;
-	else {
+	pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
+	if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
+		if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
+			dev->ltr_path = 1;
+			return;
+		}
+
 		bridge = pci_upstream_bridge(dev);
 		if (bridge && bridge->ltr_path)
 			dev->ltr_path = 1;
+
+		return;
 	}
 
-	if (dev->ltr_path)
+	if (!host->native_ltr)
+		return;
+
+	/*
+	 * Software must not enable LTR in an Endpoint unless the Root
+	 * Complex and all intermediate Switches indicate support for LTR.
+	 * PCIe r4.0, sec 6.18.
+	 */
+	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
+	    ((bridge = pci_upstream_bridge(dev)) &&
+	      bridge->ltr_path)) {
 		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
 					 PCI_EXP_DEVCTL2_LTR_EN);
+		dev->ltr_path = 1;
+	}
 #endif
 }
 

[PATCH v1 2/2] PCI/ASPM: Save LTR Capability for suspend/resume

[Bjorn Helgaas]

From: Bjorn Helgaas <bhelgaas@google.com>

Latency Tolerance Reporting (LTR) allows Endpoints and Switch Upstream
Ports to report their latency requirements to upstream components.  If ASPM
L1 PM substates are enabled, the LTR information helps determine when a
Link enters L1.2 [1].

Software must set the maximum latency values in the LTR Capability based on
characteristics of the platform, then set LTR Mechanism Enable in the
Device Control 2 register in the PCIe Capability.  The device can then use
LTR to report its latency tolerance.

If the device reports a maximum latency value of zero, that means the
device requires the highest possible performance and the ASPM L1.2 substate
is effectively disabled.

We put devices in D3 for suspend, and we assume their internal state is
lost.  On resume, previously we did not restore the LTR Capability, but we
did restore the LTR Mechanism Enable bit, so devices would request the
highest possible performance and ASPM L1.2 wouldn't be used.

[1] PCIe r4.0, sec 5.5.1
Link: https://bugzilla.kernel.org/show_bug.cgi?id=201469
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/pci.c |   53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index c9d8e3c837de..13d65991c77b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1233,7 +1233,6 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
 	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
 }
 
-
 static int pci_save_pcix_state(struct pci_dev *dev)
 {
 	int pos;
@@ -1270,6 +1269,45 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
 	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
 }
 
+static void pci_save_ltr_state(struct pci_dev *dev)
+{
+	int ltr;
+	struct pci_cap_saved_state *save_state;
+	u16 *cap;
+
+	if (!pci_is_pcie(dev))
+		return;
+
+	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
+	if (!ltr)
+		return;
+
+	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
+	if (!save_state) {
+		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
+		return;
+	}
+
+	cap = (u16 *)&save_state->cap.data[0];
+	pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
+	pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
+}
+
+static void pci_restore_ltr_state(struct pci_dev *dev)
+{
+	struct pci_cap_saved_state *save_state;
+	int ltr;
+	u16 *cap;
+
+	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
+	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
+	if (!save_state || !ltr)
+		return;
+
+	cap = (u16 *)&save_state->cap.data[0];
+	pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
+	pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
+}
 
 /**
  * pci_save_state - save the PCI configuration space of a device before suspending
@@ -1291,6 +1329,7 @@ int pci_save_state(struct pci_dev *dev)
 	if (i != 0)
 		return i;
 
+	pci_save_ltr_state(dev);
 	pci_save_dpc_state(dev);
 	return pci_save_vc_state(dev);
 }
@@ -1390,7 +1429,12 @@ void pci_restore_state(struct pci_dev *dev)
 	if (!dev->state_saved)
 		return;
 
-	/* PCI Express register must be restored first */
+	/*
+	 * Restore max latencies (in the LTR capability) before enabling
+	 * LTR itself (in the PCIe capability).
+	 */
+	pci_restore_ltr_state(dev);
+
 	pci_restore_pcie_state(dev);
 	pci_restore_pasid_state(dev);
 	pci_restore_pri_state(dev);
@@ -2998,6 +3042,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
 	if (error)
 		pci_err(dev, "unable to preallocate PCI-X save buffer\n");
 
+	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
+					    2 * sizeof(u16));
+	if (error)
+		pci_err(dev, "unable to allocate suspend buffer for LTR\n");
+
 	pci_allocate_vc_save_buffers(dev);
 }
 

Re: [PATCH v1 2/2] PCI/ASPM: Save LTR Capability for suspend/resume

[Vidya Sagar]

On 2/12/2019 4:25 AM, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> Latency Tolerance Reporting (LTR) allows Endpoints and Switch Upstream
> Ports to report their latency requirements to upstream components.  If ASPM
> L1 PM substates are enabled, the LTR information helps determine when a
> Link enters L1.2 [1].
>
> Software must set the maximum latency values in the LTR Capability based on
> characteristics of the platform, then set LTR Mechanism Enable in the
> Device Control 2 register in the PCIe Capability.  The device can then use
> LTR to report its latency tolerance.
>
> If the device reports a maximum latency value of zero, that means the
> device requires the highest possible performance and the ASPM L1.2 substate
> is effectively disabled.
>
> We put devices in D3 for suspend, and we assume their internal state is
> lost.  On resume, previously we did not restore the LTR Capability, but we
> did restore the LTR Mechanism Enable bit, so devices would request the
> highest possible performance and ASPM L1.2 wouldn't be used.
>
> [1] PCIe r4.0, sec 5.5.1
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=201469
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
>   drivers/pci/pci.c |   53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index c9d8e3c837de..13d65991c77b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1233,7 +1233,6 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
>   	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
>   }
>   
> -
>   static int pci_save_pcix_state(struct pci_dev *dev)
>   {
>   	int pos;
> @@ -1270,6 +1269,45 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
>   	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
>   }
>   
> +static void pci_save_ltr_state(struct pci_dev *dev)
> +{
> +	int ltr;
> +	struct pci_cap_saved_state *save_state;
> +	u16 *cap;
> +
> +	if (!pci_is_pcie(dev))
> +		return;
> +
> +	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
> +	if (!ltr)
> +		return;
> +
> +	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> +	if (!save_state) {
> +		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
> +		return;
> +	}
> +
> +	cap = (u16 *)&save_state->cap.data[0];
> +	pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
> +	pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
> +}
> +
> +static void pci_restore_ltr_state(struct pci_dev *dev)
> +{
> +	struct pci_cap_saved_state *save_state;
> +	int ltr;
> +	u16 *cap;
> +
> +	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> +	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
> +	if (!save_state || !ltr)
> +		return;
> +
> +	cap = (u16 *)&save_state->cap.data[0];
> +	pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
> +	pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
> +}
>   
>   /**
>    * pci_save_state - save the PCI configuration space of a device before suspending
> @@ -1291,6 +1329,7 @@ int pci_save_state(struct pci_dev *dev)
>   	if (i != 0)
>   		return i;
>   
> +	pci_save_ltr_state(dev);
>   	pci_save_dpc_state(dev);
>   	return pci_save_vc_state(dev);
>   }
> @@ -1390,7 +1429,12 @@ void pci_restore_state(struct pci_dev *dev)
>   	if (!dev->state_saved)
>   		return;
>   
> -	/* PCI Express register must be restored first */
> +	/*
> +	 * Restore max latencies (in the LTR capability) before enabling
> +	 * LTR itself (in the PCIe capability).
> +	 */
> +	pci_restore_ltr_state(dev);
> +
>   	pci_restore_pcie_state(dev);
>   	pci_restore_pasid_state(dev);
>   	pci_restore_pri_state(dev);
> @@ -2998,6 +3042,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
>   	if (error)
>   		pci_err(dev, "unable to preallocate PCI-X save buffer\n");
>   
> +	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
> +					    2 * sizeof(u16));
> +	if (error)
> +		pci_err(dev, "unable to allocate suspend buffer for LTR\n");
> +
>   	pci_allocate_vc_save_buffers(dev);
>   }
Don't we have to save and restore L1SS control registers (PCI_L1SS_CTL1 
& PCI_L1SS_CTL2) as well?
>   
>

Re: [PATCH v1 2/2] PCI/ASPM: Save LTR Capability for suspend/resume

[Bjorn Helgaas]

On Wed, Feb 13, 2019 at 10:53:01AM +0530, Vidya Sagar wrote:
> On 2/12/2019 4:25 AM, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas <bhelgaas@google.com>
> > 
> > Latency Tolerance Reporting (LTR) allows Endpoints and Switch Upstream
> > Ports to report their latency requirements to upstream components.  If ASPM
> > L1 PM substates are enabled, the LTR information helps determine when a
> > Link enters L1.2 [1].
> > 
> > Software must set the maximum latency values in the LTR Capability based on
> > characteristics of the platform, then set LTR Mechanism Enable in the
> > Device Control 2 register in the PCIe Capability.  The device can then use
> > LTR to report its latency tolerance.
> > 
> > If the device reports a maximum latency value of zero, that means the
> > device requires the highest possible performance and the ASPM L1.2 substate
> > is effectively disabled.
> > 
> > We put devices in D3 for suspend, and we assume their internal state is
> > lost.  On resume, previously we did not restore the LTR Capability, but we
> > did restore the LTR Mechanism Enable bit, so devices would request the
> > highest possible performance and ASPM L1.2 wouldn't be used.
> > 
> > [1] PCIe r4.0, sec 5.5.1
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=201469
> > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > ---
> >   drivers/pci/pci.c |   53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
> >   1 file changed, 51 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index c9d8e3c837de..13d65991c77b 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -1233,7 +1233,6 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
> >   	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
> >   }
> > -
> >   static int pci_save_pcix_state(struct pci_dev *dev)
> >   {
> >   	int pos;
> > @@ -1270,6 +1269,45 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
> >   	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
> >   }
> > +static void pci_save_ltr_state(struct pci_dev *dev)
> > +{
> > +	int ltr;
> > +	struct pci_cap_saved_state *save_state;
> > +	u16 *cap;
> > +
> > +	if (!pci_is_pcie(dev))
> > +		return;
> > +
> > +	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
> > +	if (!ltr)
> > +		return;
> > +
> > +	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> > +	if (!save_state) {
> > +		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
> > +		return;
> > +	}
> > +
> > +	cap = (u16 *)&save_state->cap.data[0];
> > +	pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
> > +	pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
> > +}
> > +
> > +static void pci_restore_ltr_state(struct pci_dev *dev)
> > +{
> > +	struct pci_cap_saved_state *save_state;
> > +	int ltr;
> > +	u16 *cap;
> > +
> > +	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
> > +	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
> > +	if (!save_state || !ltr)
> > +		return;
> > +
> > +	cap = (u16 *)&save_state->cap.data[0];
> > +	pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
> > +	pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
> > +}
> >   /**
> >    * pci_save_state - save the PCI configuration space of a device before suspending
> > @@ -1291,6 +1329,7 @@ int pci_save_state(struct pci_dev *dev)
> >   	if (i != 0)
> >   		return i;
> > +	pci_save_ltr_state(dev);
> >   	pci_save_dpc_state(dev);
> >   	return pci_save_vc_state(dev);
> >   }
> > @@ -1390,7 +1429,12 @@ void pci_restore_state(struct pci_dev *dev)
> >   	if (!dev->state_saved)
> >   		return;
> > -	/* PCI Express register must be restored first */
> > +	/*
> > +	 * Restore max latencies (in the LTR capability) before enabling
> > +	 * LTR itself (in the PCIe capability).
> > +	 */
> > +	pci_restore_ltr_state(dev);
> > +
> >   	pci_restore_pcie_state(dev);
> >   	pci_restore_pasid_state(dev);
> >   	pci_restore_pri_state(dev);
> > @@ -2998,6 +3042,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
> >   	if (error)
> >   		pci_err(dev, "unable to preallocate PCI-X save buffer\n");
> > +	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
> > +					    2 * sizeof(u16));
> > +	if (error)
> > +		pci_err(dev, "unable to allocate suspend buffer for LTR\n");
> > +
> >   	pci_allocate_vc_save_buffers(dev);
> >   }

> Don't we have to save and restore L1SS control registers (PCI_L1SS_CTL1 &
> PCI_L1SS_CTL2) as well?

I think you're right!  It's getting embarrassing how much stuff we
missed.  I'll work on this, and look for other capabilities where we
might be missing save/restore.

Bjorn

Re: [PATCH v1 0/2] PCI/ASPM: Fix LTR issues

[Bjorn Helgaas]

On Mon, Feb 11, 2019 at 04:55:33PM -0600, Bjorn Helgaas wrote:
> These are to fix a couple LTR-related issues found while investigating
> https://bugzilla.kernel.org/show_bug.cgi?id=201469
> 
> I don't claim that these fix the whole problem of that bugzilla, but I
> think it's pretty clear that these are problems we need to fix, so I want
> to give these a little more exposure.
> 
> Feedback welcome!
> 
> ---
> 
> Bjorn Helgaas (2):
>       PCI/ASPM: Use LTR if already enabled by platform
>       PCI/ASPM: Save LTR Capability for suspend/resume
> 
> 
>  drivers/pci/pci.c   |   53 +++++++++++++++++++++++++++++++++++++++++++++++++--
>  drivers/pci/probe.c |   36 ++++++++++++++++++++++-------------
>  2 files changed, 74 insertions(+), 15 deletions(-)

I applied these to pci/aspm for v5.1.

I think Vidya is absolutely right that we also need to save/restore
the ASPM L1 Substates capability.  But I haven't had a chance to
write that up yet, and I think these two patches by themselves
are an improvement even without ASPM L1 SS.

Bjorn

Re: [PATCH v1 0/2] PCI/ASPM: Fix LTR issues

[Rafael J. Wysocki]

On Friday, February 22, 2019 5:58:24 AM CET Bjorn Helgaas wrote:
> On Mon, Feb 11, 2019 at 04:55:33PM -0600, Bjorn Helgaas wrote:
> > These are to fix a couple LTR-related issues found while investigating
> > https://bugzilla.kernel.org/show_bug.cgi?id=201469
> > 
> > I don't claim that these fix the whole problem of that bugzilla, but I
> > think it's pretty clear that these are problems we need to fix, so I want
> > to give these a little more exposure.
> > 
> > Feedback welcome!
> > 
> > ---
> > 
> > Bjorn Helgaas (2):
> >       PCI/ASPM: Use LTR if already enabled by platform
> >       PCI/ASPM: Save LTR Capability for suspend/resume
> > 
> > 
> >  drivers/pci/pci.c   |   53 +++++++++++++++++++++++++++++++++++++++++++++++++--
> >  drivers/pci/probe.c |   36 ++++++++++++++++++++++-------------
> >  2 files changed, 74 insertions(+), 15 deletions(-)
> 
> I applied these to pci/aspm for v5.1.
> 
> I think Vidya is absolutely right that we also need to save/restore
> the ASPM L1 Substates capability.  But I haven't had a chance to
> write that up yet, and I think these two patches by themselves
> are an improvement even without ASPM L1 SS.

Agreed.

Cheers,
Rafael