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From: Bjorn Helgaas <helgaas@kernel.org>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Leo Li <leoyang.li@nxp.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"M.h. Lian" <minghuan.lian@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
Date: Mon, 11 Mar 2019 12:34:39 -0500
Message-ID: <20190311173439.GH214730@google.com> (raw)
In-Reply-To: <20190311093130.7209-27-Zhiqiang.Hou@nxp.com>

On Mon, Mar 11, 2019 at 09:33:32AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> When LX2 PCIe controller is sending multiple split completions and
> ACK latency expires indicating that ACK should be send at priority.
> But because of large number of split completions and FC update DLLP,
> the controller does not give priority to ACK transmission. This
> results into ACK latency timer timeout error at the link partner and
> the pending TLPs are replayed by the link partner again.
> 
> Workaround:
> 1. Reduce the ACK latency timeout value to a very small value.
> 2. Restrict the number of completions from the LX2 PCIe controller
>    to 1, by changing the Max Read Request Size (MRRS) of link partner
>    to the same value as Max Packet size (MPS).
> 
> This patch implemented part 1, the part 2 can be set by kernel parameter
> 'pci=pcie_bus_perf'

If I understand correctly, you're saying that LX2160A Rev1.0 will only
work correctly if you have this patch applied AND you boot with
"pci=pcie_bus_perf".

That might be OK if these rev 1.0 parts are only used in the lab and
are never shipped to customers.  But if these parts are ever shipped
to customers, I don't think it's acceptable for them to have to figure
out that they must boot with "pci=pcie_bus_perf".  Yes, you can
document that in release notes, but it's still a poor user experience,
and users will forget, and they will see mysterious hard-to-debug
issues.

Maybe there's a way for you to automatically set that pcie_bus_perf
mode?  With a dmesg note to indicate that you're overriding any mode
the user may have selected?

> This ERRATA is only for LX2160A Rev1.0, and it will be fixed
> in Rev2.0.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
>  - no change
> 
>  .../pci/controller/mobiveil/pci-layerscape-gen4.c | 15 +++++++++++++++
>  drivers/pci/controller/mobiveil/pcie-mobiveil.h   |  4 ++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> index d2c5dbbd5e3c..20ce146788ca 100644
> --- a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -82,12 +82,27 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
>  	return header_type == PCI_HEADER_TYPE_BRIDGE;
>  }
>  
> +static void workaround_A011451(struct ls_pcie_g4 *pcie)
> +{
> +	struct mobiveil_pcie *mv_pci = pcie->pci;
> +	u32 val;
> +
> +	/* Set ACK latency timeout */
> +	val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
> +	val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
> +	val |= (4 << ACK_LAT_TO_VAL_SHIFT);
> +	csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
> +}
> +
>  static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
>  {
>  	struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
>  
>  	pcie->rev = csr_readb(pci, PCI_REVISION_ID);
>  
> +	if (pcie->rev == REV_1_0)
> +		workaround_A011451(pcie);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index ab43de5e4b2b..f0e2e4ae09b5 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -85,6 +85,10 @@
>  #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
>  #define PAB_INTP_AXI_PIO_CLASS		0x474
>  
> +#define GPEX_ACK_REPLAY_TO		0x438
> +#define  ACK_LAT_TO_VAL_MASK		0x1fff
> +#define  ACK_LAT_TO_VAL_SHIFT		0
> +
>  #define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
>  #define  AMAP_CTRL_EN_SHIFT		0
>  #define  AMAP_CTRL_TYPE_SHIFT		1
> -- 
> 2.17.1
> 

  reply index

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-11  9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 01/28] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 02/28] PCI: mobiveil: format the code without function change Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 03/28] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 04/28] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 05/28] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 06/28] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-03-11  9:30 ` [PATCHv4 07/28] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 08/28] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 09/28] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-03-11 14:08   ` Bjorn Helgaas
2019-03-12  4:42     ` Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-03-11 14:14   ` Bjorn Helgaas
2019-03-12  9:17     ` Z.q. Hou
2019-03-13 10:59       ` Subrahmanya Lingappa
2019-03-11  9:31 ` [PATCHv4 12/28] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 13/28] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 14/28] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-03-11  9:31 ` [PATCHv4 15/28] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 16/28] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-03-26 17:34   ` Lorenzo Pieralisi
2019-03-27  2:04     ` Z.q. Hou
2019-03-27 17:39       ` Lorenzo Pieralisi
2019-03-28  2:09         ` Z.q. Hou
2019-03-28 16:09           ` Lorenzo Pieralisi
2019-03-29  6:07             ` Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 17/28] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 18/28] PCI: mobiveil: add link up condition check Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 19/28] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-03-11  9:32 ` [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-03-11 22:11   ` Rob Herring
2019-03-12  3:17     ` Z.q. Hou
2019-03-12  9:42   ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 24/28] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11 14:01   ` Bjorn Helgaas
2019-03-12  4:40     ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-03-13 14:51   ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-03-11 17:34   ` Bjorn Helgaas [this message]
2019-03-12  9:34     ` Z.q. Hou
2019-03-12 13:34       ` Bjorn Helgaas
2019-03-13 14:49         ` Z.q. Hou
2019-03-13 14:51   ` Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-03-11  9:33 ` [PATCHv4 28/28] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-03-11 13:33 ` [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Bjorn Helgaas
2019-03-12  4:18   ` Z.q. Hou
2019-03-26 17:37 ` Lorenzo Pieralisi
2019-03-27  2:11   ` Z.q. Hou

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