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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id o15sm34817870wrj.59.2019.04.11.03.13.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Apr 2019 03:13:54 -0700 (PDT) Date: Thu, 11 Apr 2019 12:13:53 +0200 From: Thierry Reding To: Vidya Sagar Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, lorenzo.pieralisi@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V2 01/16] PCI: Add #defines for PCIe spec r4.0 features Message-ID: <20190411101353.GE4633@ulmo> References: <1554407683-31580-1-git-send-email-vidyas@nvidia.com> <1554407683-31580-2-git-send-email-vidyas@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ZInfyf7laFu/Kiw7" Content-Disposition: inline In-Reply-To: <1554407683-31580-2-git-send-email-vidyas@nvidia.com> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --ZInfyf7laFu/Kiw7 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Apr 05, 2019 at 01:24:28AM +0530, Vidya Sagar wrote: > Add #defines for the Data Link Feature and Physical Layer 16.0 GT/s > features. >=20 > Signed-off-by: Vidya Sagar > --- > Changes from [v1]: > * None >=20 > include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) >=20 > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 5c98133f2c94..3e01b55d548d 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -705,7 +705,9 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM > +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > +#define PCI_EXT_CAP_ID_PL 0x26 /* Physical Layer 16.0 GT/s */ > +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL > =20 > #define PCI_EXT_CAP_DSN_SIZEOF 12 > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > @@ -1045,4 +1047,22 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOL= D_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > =20 > +/* Data Link Feature */ > +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ > +#define PCI_DLF_LOCAL_DLF_SUP_MASK 0x007fffff /* Local Data Link Featu= re Supported */ > +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchan= ge Enable */ > +#define PCI_DLF_STS 0x08 /* Status Register */ > +#define PCI_DLF_REMOTE_DLF_SUP_MASK 0x007fffff /* Remote Data Link Fea= ture Supported */ > +#define PCI_DLF_REMOTE_DLF_SUP_VALID 0x80000000 /* Remote Data Link Fe= ature Support Valid */ > + > +/* Physical Layer 16.0 GT/s */ > +#define PCI_PL_16GT_CAP 0x04 /* Capabilities Register */ > +#define PCI_PL_16GT_CTRL 0x08 /* Control Register */ > +#define PCI_PL_16GT_STS 0x0c /* Status Register */ > +#define PCI_PL_16GT_LDPM_STS 0x10 /* Local Data Parity Mismatch Status R= egister */ > +#define PCI_PL_16GT_FRDPM_STS 0x14 /* First Retimer Data Parity Mismatch= Status Register */ > +#define PCI_PL_16GT_SRDPM_STS 0x18 /* Second Retimer Data Parity Mismatc= h Status Register */ > +#define PCI_PL_16GT_RSVD 0x1C /* Reserved */ > +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ This looks correct comparing to the specification. However, this leaves out some definitions, so I'm wondering if perhaps this should include all field definitions. There are also extended capabilities between the current maximum 0x1F and 0x25. Perhaps those should be added as well. I guess this could always be done as a follow-up. Perhaps it'd be better to change the subject to more accurately reflect that you're only adding a couple of PCIe 4.0 features. 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