From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8300BC10F14 for ; Thu, 11 Apr 2019 17:05:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 50DC320818 for ; Thu, 11 Apr 2019 17:05:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="F3ELa1ji" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726968AbfDKRF3 (ORCPT ); Thu, 11 Apr 2019 13:05:29 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7142 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726585AbfDKRF3 (ORCPT ); Thu, 11 Apr 2019 13:05:29 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:05:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:05:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:05:28 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:05:28 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:05:28 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:05:25 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 16/30] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Date: Thu, 11 Apr 2019 22:33:41 +0530 Message-ID: <20190411170355.6882-17-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002326; bh=aCV3jISdvVgfuMdoLHQA8F7pI8usjEAzqgQaE1nKx7k=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=F3ELa1jiISVsw8UrQPMCR/Wa/nkK+1gh2HfZLCqTjEGCj2q5I07A8U3eKSC3vI3YH fhwCZIYRTFbp5nkJekClneidt1M8AN7E5yR7bSAZFRmP9EZLxhlLLOCGou9cEUoUHf 76hH3hC231TExrd6DSd0ZImPDeBPYq6mZQUAXadnjw8YWuuG5NK8YmribnY/iGMgMJ tYc/p/EHl9NC2Un7Yxtm9r0CaNfEfKyVaBwWQ+h51RtWpi3tRzFC6orcpOZef67B2k 8SJ63//3bGWnt4S7ysGyMTKJFgWOYgPAVO7XxOHYF2UAB9FjDEVf1OOp0iVqQxaw8W nXDHY0VMsiXcA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org AFI_CACHE* registers are available only in Tegra20, program them only for Tegra20. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/pci-tegra.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 8e5fdc8ce3d6..cdaaf13a9fd7 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -887,6 +887,7 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg) */ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) { + struct device_node *np = pcie->dev->of_node; u32 fpci_bar, size, axi_address; /* Bar 0: type 1 extended configuration space */ @@ -927,11 +928,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); afi_writel(pcie, 0, AFI_FPCI_BAR5); - /* map all upstream transactions as uncached */ - afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); - afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); - afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { + /* map all upstream transactions as uncached */ + afi_writel(pcie, 0, AFI_CACHE_BAR0_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); + afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); + afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); + } /* MSI translations are setup only when needed */ afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); -- 2.17.1