From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5284EC10F14 for ; Thu, 11 Apr 2019 17:06:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1E1C8217D4 for ; Thu, 11 Apr 2019 17:06:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="AwnhbnUM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726951AbfDKRGA (ORCPT ); Thu, 11 Apr 2019 13:06:00 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15334 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726667AbfDKRGA (ORCPT ); Thu, 11 Apr 2019 13:06:00 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:05:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:05:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:05:59 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:05:59 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:05:55 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 23/30] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Date: Thu, 11 Apr 2019 22:33:48 +0530 Message-ID: <20190411170355.6882-24-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002343; bh=LOih456DDfF0v6aQUvlH2t266NwLJs0yOKIpBqkweJs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AwnhbnUMq1ayo6BRjLxs/bVTuMxK/bmT5asyv5UYnLty8fnoxnBeHvbZ8EDxkoIkq KKnzCmUGtyUvtNTly5UGlD2vI8qWda+u6Epq+VvhOs9oJgk/WnXxwjiliS7RMPnQCW XhCLlcGLiC4Oo+i1jJ2yft66MbNE1iRygfX0sgorY+0m2nIP3im9PxIj7Klvq77tDi /smvjf0ZZzKt1w20ut1TJLw4ujt7/K56P0+ijEjYMfyyLgcO5ESdZz2Vu/ZFg24TvM yBbIsPod9NIv8iD/Eni2vLi6HlbwPmS/i8mKySLIaZjE452UH37Akb0f4/7NslgJHS yWtt4FHdzqAhw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document PCIe DPD pinctrl optional property to put PEX clk & BIAS pads in low power mode. Signed-off-by: Manikanta Maddireddy --- .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 145a4f04194f..fbbd3bcb3435 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -65,6 +65,15 @@ Required properties: - afi - pcie_x +Optional properties: +- pinctrl-names : The pin control state names. +- pinctrl-0: PCIe IO(bias & REFCLK) deep power down(DPD) disable state. + In Tegra210 PCIe clamps are not controlling IO signals, so there + is leakagae power even after PCIe power partition is off. Pass + pinctrl phandle to allow driver to explicitly put PCIe IO in DPD state. +- pinctrl-1: PCIe IO(bias & REFCLK) deep power down(DPD) enable state. + Pass pinctrl phandle to allow driver bring PCIe IO out of DPD state. + Required properties on Tegra124 and later (deprecated): - phys: Must contain an entry for each entry in phy-names. - phy-names: Must include the following entries: -- 2.17.1