From: "Z.q. Hou" <zhiqiang.hou@nxp.com> To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "bhelgaas@google.com" <bhelgaas@google.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Leo Li <leoyang.li@nxp.com>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com> Cc: Mingkai Hu <mingkai.hu@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>, Xiaowei Bao <xiaowei.bao@nxp.com>, "Z.q. Hou" <zhiqiang.hou@nxp.com> Subject: [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Date: Fri, 12 Apr 2019 08:36:42 +0000 Message-ID: <20190412083635.33626-16-Zhiqiang.Hou@nxp.com> (raw) In-Reply-To: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Allow CFG transactions to all functions of Endpoint implemented multiple functions. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> --- V5: - Corrected and retouched the subject and changelog. drivers/pci/controller/pcie-mobiveil.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c index 9210165fe8c0..621852078caf 100644 --- a/drivers/pci/controller/pcie-mobiveil.c +++ b/drivers/pci/controller/pcie-mobiveil.c @@ -291,7 +291,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) * Do not read more than one device on the bus directly * attached to RC */ - if ((bus->primary == pcie->root_bus_nr) && (devfn > 0)) + if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0)) return false; return true; -- 2.17.1
next prev parent reply index Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-12 8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou 2019-07-03 15:10 ` Lorenzo Pieralisi 2019-07-04 2:41 ` Z.q. Hou 2019-07-03 15:19 ` Lorenzo Pieralisi 2019-07-03 15:24 ` Lorenzo Pieralisi 2019-07-04 3:00 ` Z.q. Hou 2019-07-04 10:56 ` Lorenzo Pieralisi 2019-07-05 2:24 ` Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou 2019-07-03 14:17 ` Lorenzo Pieralisi 2019-07-04 2:38 ` Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou 2019-06-11 16:59 ` Lorenzo Pieralisi 2019-06-11 17:29 ` Marc Zyngier 2019-06-12 10:54 ` Lorenzo Pieralisi 2019-06-12 11:22 ` Marc Zyngier 2019-06-12 11:34 ` Z.q. Hou 2019-06-12 13:08 ` Lorenzo Pieralisi 2019-06-15 1:30 ` Z.q. Hou 2019-06-17 9:33 ` Lorenzo Pieralisi 2019-06-17 10:34 ` Z.q. Hou 2019-06-28 11:35 ` Lorenzo Pieralisi 2019-07-01 10:07 ` Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou 2019-04-12 8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou 2019-06-12 15:13 ` Lorenzo Pieralisi 2019-04-12 8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou 2019-06-28 16:02 ` Lorenzo Pieralisi 2019-07-01 10:18 ` Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou 2019-06-28 16:41 ` Lorenzo Pieralisi 2019-07-01 10:24 ` Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou 2019-06-12 15:08 ` Lorenzo Pieralisi 2019-06-14 7:08 ` Karthikeyan Mitran 2019-06-14 10:43 ` Lorenzo Pieralisi 2019-06-19 5:28 ` Karthikeyan Mitran 2019-06-19 7:24 ` Z.q. Hou 2019-06-28 17:05 ` Lorenzo Pieralisi 2019-07-01 10:27 ` Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou 2019-04-12 8:36 ` Z.q. Hou [this message] 2019-04-12 8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou 2019-06-11 17:17 ` Lorenzo Pieralisi 2019-06-12 11:36 ` Z.q. Hou 2019-04-12 8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou 2019-06-12 14:34 ` Lorenzo Pieralisi 2019-06-15 2:34 ` Z.q. Hou 2019-04-12 8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou 2019-06-12 16:23 ` Lorenzo Pieralisi 2019-06-15 5:03 ` Z.q. Hou 2019-06-17 9:30 ` Lorenzo Pieralisi 2019-06-17 10:42 ` Z.q. Hou 2019-04-12 8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou 2019-06-12 13:54 ` Lorenzo Pieralisi 2019-06-15 1:13 ` Z.q. Hou 2019-06-17 9:29 ` Lorenzo Pieralisi 2019-06-17 10:16 ` Z.q. Hou 2019-04-12 8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou 2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi 2019-07-04 2:36 ` Z.q. Hou
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20190412083635.33626-16-Zhiqiang.Hou@nxp.com \ --to=zhiqiang.hou@nxp.com \ --cc=bhelgaas@google.com \ --cc=catalin.marinas@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=l.subrahmanya@mobiveil.co.in \ --cc=leoyang.li@nxp.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=mark.rutland@arm.com \ --cc=minghuan.lian@nxp.com \ --cc=mingkai.hu@nxp.com \ --cc=robh+dt@kernel.org \ --cc=shawnguo@kernel.org \ --cc=will.deacon@arm.com \ --cc=xiaowei.bao@nxp.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
Linux-PCI Archive on lore.kernel.org Archives are clonable: git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git # If you have public-inbox 1.1+ installed, you may # initialize and index your mirror using the following commands: public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \ linux-pci@vger.kernel.org public-inbox-index linux-pci Example config snippet for mirrors Newsgroup available over NNTP: nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci AGPL code for this site: git clone https://public-inbox.org/public-inbox.git