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[46.91.230.29]) by smtp.gmail.com with ESMTPSA id v184sm33476587wma.6.2019.04.15.04.41.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Apr 2019 04:41:59 -0700 (PDT) Date: Mon, 15 Apr 2019 13:41:58 +0200 From: Thierry Reding To: Manikanta Maddireddy Cc: Bjorn Helgaas , robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations Message-ID: <20190415114158.GM29254@ulmo> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> <20190411170355.6882-13-mmaddireddy@nvidia.com> <20190411200121.GQ256045@google.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="dp9QYJgVRVEW2bsm" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Archived-At: List-Archive: List-Post: --dp9QYJgVRVEW2bsm Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Apr 12, 2019 at 11:29:35AM +0530, Manikanta Maddireddy wrote: >=20 > On 12-Apr-19 1:31 AM, Bjorn Helgaas wrote: > > On Thu, Apr 11, 2019 at 10:33:37PM +0530, Manikanta Maddireddy wrote: > >> The logic which blocks read requests till AFI gets ACK for all outstan= ding > >> MC writes does not behave correctly when number of outstanding write > >> becomes more than 32 in Tegra124 and 132. > >> > >> SW fixup to prevent this issue is to limit outstanding posted writes a= nd > >> tweak updateFC timer threshold. > >> > >> Signed-off-by: Manikanta Maddireddy > >> static void tegra_pcie_port_enable(struct tegra_pcie_port *port) > >> @@ -2381,6 +2408,7 @@ static const struct tegra_pcie_soc tegra20_pcie = =3D { > >> .program_uphy =3D true, > >> .update_clamp_threshold =3D false, > >> .program_deskew_time =3D false, > >> + .raw_violation_fixup =3D false, > >> .ectl.enable =3D false, > > It doesn't really matter either way, but you don't *have* to > > initialize all these flags to "false" since that's the default for > > uninitialized fields in static structs like these. If you left them > > out, the structs would only contain the "true" items, and it'd be > > easier to see what's special about each SoC. >=20 > SoC flags are explicitly set false if not supported, I am following > same existing coding style in this driver. Maybe the intention here is > to convey what is not supported by a particular SoC without going > through soc struct definition. Yes, this was originally done on purpose. I think it's good to follow the existing convention, unless Bjorn feels strongly about it. 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