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From: Thierry Reding <thierry.reding@gmail.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
	jonathanh@nvidia.com, lorenzo.pieralisi@arm.com,
	vidyas@nvidia.com, linux-tegra@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 06/30] PCI: tegra: Program UPHY electrical settings for Tegra210
Date: Mon, 15 Apr 2019 17:38:14 +0200
Message-ID: <20190415153814.GM29254@ulmo> (raw)
In-Reply-To: <f8c52bea-4e78-0f50-54ee-d8b41ec1b3d1@nvidia.com>

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On Mon, Apr 15, 2019 at 08:25:48PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 15-Apr-19 4:59 PM, Thierry Reding wrote:
> > On Thu, Apr 11, 2019 at 10:33:31PM +0530, Manikanta Maddireddy wrote:
> >> UPHY electrical programming guidelines are documented in Tegra210 TRM.
> >> Program these electrical settings for proper eye diagram in Gen1 and Gen2
> >> link speeds.
> >>
> >> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> >> ---
> >>  drivers/pci/controller/pci-tegra.c | 100 +++++++++++++++++++++++++++++
> >>  1 file changed, 100 insertions(+)
> >>
> >> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> >> index 9ff1a0e2797f..a377245d254d 100644
> >> --- a/drivers/pci/controller/pci-tegra.c
> >> +++ b/drivers/pci/controller/pci-tegra.c
> >> @@ -177,6 +177,32 @@
> >>  
> >>  #define AFI_PEXBIAS_CTRL_0		0x168
> >>  
> >> +#define RP_ECTL_2_R1	0x00000e84
> >> +#define  RP_ECTL_2_R1_RX_CTLE_1C_MASK		0xffff
> >> +
> >> +#define RP_ECTL_4_R1	0x00000e8c
> >> +#define  RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK	(0xffff << 16)
> >> +#define  RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT	16
> >> +
> >> +#define RP_ECTL_5_R1	0x00000e90
> >> +#define  RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK	0xffffffff
> >> +
> >> +#define RP_ECTL_6_R1	0x00000e94
> >> +#define  RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK	0xffffffff
> >> +
> >> +#define RP_ECTL_2_R2	0x00000ea4
> >> +#define  RP_ECTL_2_R2_RX_CTLE_1C_MASK	0xffff
> >> +
> >> +#define RP_ECTL_4_R2	0x00000eac
> >> +#define  RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK	(0xffff << 16)
> >> +#define  RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT	16
> >> +
> >> +#define RP_ECTL_5_R2	0x00000eb0
> >> +#define  RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK	0xffffffff
> >> +
> >> +#define RP_ECTL_6_R2	0x00000eb4
> >> +#define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK	0xffffffff
> >> +
> >>  #define RP_VEND_XP	0x00000f00
> >>  #define  RP_VEND_XP_DL_UP	(1 << 30)
> >>  
> >> @@ -265,6 +291,19 @@ struct tegra_pcie_soc {
> >>  	bool has_gen2;
> >>  	bool force_pca_enable;
> >>  	bool program_uphy;
> >> +	struct {
> >> +		struct {
> >> +			u32 rp_ectl_2_r1;
> >> +			u32 rp_ectl_4_r1;
> >> +			u32 rp_ectl_5_r1;
> >> +			u32 rp_ectl_6_r1;
> >> +			u32 rp_ectl_2_r2;
> >> +			u32 rp_ectl_4_r2;
> >> +			u32 rp_ectl_5_r2;
> >> +			u32 rp_ectl_6_r2;
> >> +		} regs;
> >> +		bool enable;
> >> +	} ectl;
> >>  };
> >>  
> >>  static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
> >> @@ -491,6 +530,52 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
> >>  	writel(value, port->base + RP_VEND_CTL1);
> >>  }
> >>  
> >> +static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
> >> +{
> >> +	const struct tegra_pcie_soc *soc = port->pcie->soc;
> >> +	u32 val;
> > u32 value for consistency.
> I will take care of it in V2
> >
> >> +
> >> +	val = readl(port->base + RP_ECTL_2_R1);
> >> +	val &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_2_r1;
> >> +	writel(val, port->base + RP_ECTL_2_R1);
> >> +
> >> +	val = readl(port->base + RP_ECTL_4_R1);
> >> +	val &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_4_r1 << RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT;
> >> +	writel(val, port->base + RP_ECTL_4_R1);
> >> +
> >> +	val = readl(port->base + RP_ECTL_5_R1);
> >> +	val &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_5_r1;
> >> +	writel(val, port->base + RP_ECTL_5_R1);
> >> +
> >> +	val = readl(port->base + RP_ECTL_6_R1);
> >> +	val &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_6_r1;
> >> +	writel(val, port->base + RP_ECTL_6_R1);
> >> +
> >> +	val = readl(port->base + RP_ECTL_2_R2);
> >> +	val &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_2_r2;
> >> +	writel(val, port->base + RP_ECTL_2_R2);
> >> +
> >> +	val = readl(port->base + RP_ECTL_4_R2);
> >> +	val &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_4_r2 << RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT;
> >> +	writel(val, port->base + RP_ECTL_4_R2);
> >> +
> >> +	val = readl(port->base + RP_ECTL_5_R2);
> >> +	val &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_5_r2;
> >> +	writel(val, port->base + RP_ECTL_5_R2);
> >> +
> >> +	val = readl(port->base + RP_ECTL_6_R2);
> >> +	val &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
> >> +	val |= soc->ectl.regs.rp_ectl_6_r2;
> >> +	writel(val, port->base + RP_ECTL_6_R2);
> > There are nice macros that help with this nowadays. See the FIELD_*
> > macros in include/linux/bitfield.h. However, the above is consistent
> > with the rest of the driver, so feel free to leave this as-is.
> I will leave it as-is to be inline with rest of the driver.
> >> +}
> >> +
> >>  static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
> >>  {
> >>  	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
> >> @@ -517,6 +602,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
> >>  	}
> >>  
> >>  	tegra_pcie_enable_rp_features(port);
> >> +	if (soc->ectl.enable)
> > An empty line above would help declutter this.
> I will take care of it in V2
> >
> >> +		tegra_pcie_program_ectl_settings(port);
> >>  }
> >>  
> >>  static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
> >> @@ -2229,6 +2316,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
> >>  	.has_gen2 = false,
> >>  	.force_pca_enable = false,
> >>  	.program_uphy = true,
> >> +	.ectl.enable = false,
> >>  };
> >>  
> >>  static const struct tegra_pcie_port_soc tegra30_pcie_ports[] = {
> >> @@ -2252,6 +2340,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
> >>  	.has_gen2 = false,
> >>  	.force_pca_enable = false,
> >>  	.program_uphy = true,
> >> +	.ectl.enable = false,
> >>  };
> >>  
> >>  static const struct tegra_pcie_soc tegra124_pcie = {
> >> @@ -2268,6 +2357,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
> >>  	.has_gen2 = true,
> >>  	.force_pca_enable = false,
> >>  	.program_uphy = true,
> >> +	.ectl.enable = false,
> >>  };
> >>  
> >>  static const struct tegra_pcie_soc tegra210_pcie = {
> >> @@ -2284,6 +2374,15 @@ static const struct tegra_pcie_soc tegra210_pcie = {
> >>  	.has_gen2 = true,
> >>  	.force_pca_enable = true,
> >>  	.program_uphy = true,
> >> +	.ectl.regs.rp_ectl_2_r1 = 0x0000000f,
> >> +	.ectl.regs.rp_ectl_4_r1 = 0x00000067,
> >> +	.ectl.regs.rp_ectl_5_r1 = 0x55010000,
> >> +	.ectl.regs.rp_ectl_6_r1 = 0x00000001,
> >> +	.ectl.regs.rp_ectl_2_r2 = 0x0000008f,
> >> +	.ectl.regs.rp_ectl_4_r2 = 0x000000c7,
> >> +	.ectl.regs.rp_ectl_5_r2 = 0x55010000,
> >> +	.ectl.regs.rp_ectl_6_r2 = 0x00000001,
> >> +	.ectl.enable = true,
> > This should be:
> >
> > 	.ectl = {
> > 		.regs = {
> > 			...
> > 		}
> > 		.enable = true;
> > 	},
> >
> > Do these parameters never differ between board layouts? Are they really
> > fixed per SoC generation?
> >
> > Thierry
> Till now all Tegra210 platform have same UPHY settings. They can differ if
> some components like MUX are added in UPHY routing, but I haven't seen
> such platforms with Tegra210.

Okay, let's leave it as SoC data for now. If we ever need to override
per board we can add that as a backward-compatible change.

Thierry

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  reply index

Thread overview: 106+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-11 17:03 [PATCH 00/30] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 01/30] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 02/30] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-04-15 11:01   ` Thierry Reding
2019-04-15 14:11     ` Manikanta Maddireddy
2019-04-15 14:30       ` Thierry Reding
2019-04-15 18:14         ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 03/30] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2019-04-15 11:06   ` Thierry Reding
2019-04-15 14:20     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 04/30] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-04-15 11:21   ` Thierry Reding
2019-04-15 14:47     ` Manikanta Maddireddy
2019-04-15 15:36       ` Thierry Reding
2019-04-15 15:53         ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 05/30] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-04-15 11:23   ` Thierry Reding
2019-04-15 14:49     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 06/30] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-04-15 11:29   ` Thierry Reding
2019-04-15 14:55     ` Manikanta Maddireddy
2019-04-15 15:38       ` Thierry Reding [this message]
2019-04-11 17:03 ` [PATCH 07/30] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2019-04-15 11:30   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 08/30] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-04-15 11:32   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 09/30] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-04-15 11:33   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 10/30] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-04-15 11:37   ` Thierry Reding
2019-04-15 14:58     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 11/30] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-04-15 11:39   ` Thierry Reding
2019-04-15 14:58     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 12/30] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-04-11 20:01   ` Bjorn Helgaas
2019-04-12  5:59     ` Manikanta Maddireddy
2019-04-15 11:41       ` Thierry Reding
2019-04-15 11:45   ` Thierry Reding
2019-04-15 15:02     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 13/30] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2019-04-15 11:47   ` Thierry Reding
2019-04-15 15:05     ` Manikanta Maddireddy
2019-04-23  9:27       ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 14/30] PCI: tegra: Set target speed as Gen1 before link up Manikanta Maddireddy
2019-04-11 20:04   ` Bjorn Helgaas
2019-04-12  6:44     ` Manikanta Maddireddy
2019-04-12 14:35       ` Bjorn Helgaas
2019-04-15 10:43         ` Manikanta Maddireddy
2019-04-15 11:52   ` Thierry Reding
2019-04-15 15:12     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 15/30] PCI: tegra: Fix PLLE powerdown issue due to CLKREQ# signal Manikanta Maddireddy
2019-04-15 13:17   ` Thierry Reding
2019-04-15 15:14     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 16/30] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-04-15 13:20   ` Thierry Reding
2019-04-16 10:47     ` Manikanta Maddireddy
2019-04-16 16:11       ` Thierry Reding
2019-04-11 17:03 ` [PATCH 17/30] PCI: tegra: Use switch statements in tegra_pcie_isr() Manikanta Maddireddy
2019-04-15 13:25   ` Thierry Reding
2019-04-15 15:25     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 18/30] PCI: tegra: Change PRSNT_SENSE irq log to debug Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 19/30] PCI: tegra: Use legacy irq for port service drivers Manikanta Maddireddy
2019-04-15 13:35   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 20/30] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-04-15 13:31   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 21/30] PCI: tegra: Add "pci" type check before parsing child device tree node Manikanta Maddireddy
2019-04-15 13:37   ` Thierry Reding
2019-04-15 15:30     ` Manikanta Maddireddy
2019-04-15 15:42       ` Thierry Reding
2019-04-11 17:03 ` [PATCH 22/30] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-04-11 20:15   ` Bjorn Helgaas
2019-04-12  7:00     ` Manikanta Maddireddy
2019-04-12 14:50       ` Bjorn Helgaas
2019-04-15 11:36         ` Manikanta Maddireddy
2019-04-15 13:45           ` Thierry Reding
2019-04-15 13:52             ` Thierry Reding
2019-04-15 14:04           ` Bjorn Helgaas
2019-04-15 15:43             ` Manikanta Maddireddy
2019-04-23 20:24               ` Bjorn Helgaas
2019-04-11 17:03 ` [PATCH 23/30] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-04-15 14:07   ` Thierry Reding
2019-04-15 15:48     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 24/30] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 25/30] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-04-15 14:11   ` Thierry Reding
2019-04-11 17:03 ` [PATCH 26/30] dt-bindings: pci: tegra: Document nvidia,plat-gpios optional prop Manikanta Maddireddy
2019-04-11 20:18   ` Bjorn Helgaas
2019-04-12  7:01     ` Manikanta Maddireddy
2019-04-15 14:16   ` Thierry Reding
2019-04-15 17:58     ` Manikanta Maddireddy
2019-04-16 15:34       ` Thierry Reding
2019-04-17 11:22         ` Manikanta Maddireddy
2019-04-17 15:19           ` Thierry Reding
2019-04-17 18:26             ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 27/30] PCI: tegra: Add support to configure platform GPIOs Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 28/30] dt-bindings: pci: tegra: Document nvidia,rst-gpio optional prop Manikanta Maddireddy
2019-04-15 14:20   ` Thierry Reding
2019-04-15 18:01     ` Manikanta Maddireddy
2019-04-29 18:33     ` Rob Herring
2019-04-11 17:03 ` [PATCH 29/30] PCI: tegra: Add support for GPIO based PCIe reset Manikanta Maddireddy
2019-04-15 14:20   ` Thierry Reding
2019-04-15 18:03     ` Manikanta Maddireddy
2019-04-11 17:03 ` [PATCH 30/30] PCI: tegra: Change link retry log level to INFO Manikanta Maddireddy
2019-04-15 14:23   ` Thierry Reding
2019-04-15 18:05     ` Manikanta Maddireddy

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