Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V6 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block
Date: Mon, 13 May 2019 10:36:21 +0530
Message-ID: <20190513050626.14991-11-vidyas@nvidia.com> (raw)
In-Reply-To: <20190513050626.14991-1-vidyas@nvidia.com>

Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys DesignWare core
based PCIe IP and Universal PHY block.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
Changes since [v5]:
* Added Sob
* Changed node name from "p2u@xxxxxxxx" to "phy@xxxxxxxx"

Changes since [v4]:
* None

Changes since [v3]:
* None

Changes since [v2]:
* Changed node label to reflect new format that includes either 'hsio' or
  'nvhs' in its name to reflect which UPHY brick they belong to

Changes since [v1]:
* This is a new patch in v2 series

 .../bindings/phy/phy-tegra194-p2u.txt         | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
new file mode 100644
index 000000000000..d23ff90baad5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
@@ -0,0 +1,28 @@
+NVIDIA Tegra194 P2U binding
+
+Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
+Speed) each interfacing with 12 and 8 P2U instances respectively.
+A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
+interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
+lane.
+
+Required properties:
+- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
+- reg: Should be the physical address space and length of respective each P2U
+       instance.
+- reg-names: Must include the entry "ctl".
+
+Required properties for PHY port node:
+- #phy-cells: Defined by generic PHY bindings.  Must be 0.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+
+p2u_hsio_0: phy@3e10000 {
+	compatible = "nvidia,tegra194-p2u";
+	reg = <0x03e10000 0x10000>;
+	reg-names = "ctl";
+
+	#phy-cells = <0>;
+};
-- 
2.17.1


  parent reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-13  5:06 [PATCH V6 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 02/15] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-05-13  7:25   ` Christoph Hellwig
2019-05-14  3:30     ` Vidya Sagar
2019-05-14  6:02       ` Christoph Hellwig
2019-05-16 13:34       ` Bjorn Helgaas
2019-05-17  8:19         ` Vidya Sagar
2019-05-17 13:24           ` Bjorn Helgaas
2019-05-17 17:53             ` Vidya Sagar
2019-05-17 18:55               ` Bjorn Helgaas
2019-05-18  1:58                 ` Vidya Sagar
2019-05-20 17:57                   ` Bjorn Helgaas
2019-05-21  5:06                     ` Vidya Sagar
2019-05-16 13:28   ` Bjorn Helgaas
2019-05-13  5:06 ` [PATCH V6 03/15] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-05-13 15:10   ` Rob Herring
2019-05-14  5:27     ` Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-05-13  5:06 ` Vidya Sagar [this message]
2019-05-13 15:22   ` [PATCH V6 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Rob Herring
2019-05-13  5:06 ` [PATCH V6 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-13  5:06 ` [PATCH V6 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190513050626.14991-11-vidyas@nvidia.com \
    --to=vidyas@nvidia.com \
    --cc=bhelgaas@google.com \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=jingoohan1@gmail.com \
    --cc=jonathanh@nvidia.com \
    --cc=kishon@ti.com \
    --cc=kthota@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=mmaddireddy@nvidia.com \
    --cc=mperttunen@nvidia.com \
    --cc=robh+dt@kernel.org \
    --cc=sagar.tv@gmail.com \
    --cc=thierry.reding@gmail.com \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org
	public-inbox-index linux-pci

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git