From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A15CBC04AB1 for ; Mon, 13 May 2019 05:08:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7114620C01 for ; Mon, 13 May 2019 05:08:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="dOxtFC2Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727575AbfEMFIa (ORCPT ); Mon, 13 May 2019 01:08:30 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12719 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726292AbfEMFI3 (ORCPT ); Mon, 13 May 2019 01:08:29 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 12 May 2019 22:08:25 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 12 May 2019 22:08:29 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 12 May 2019 22:08:29 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 05:08:29 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 13 May 2019 05:08:28 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 13 May 2019 05:08:28 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 12 May 2019 22:08:28 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH V6 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Date: Mon, 13 May 2019 10:36:23 +0530 Message-ID: <20190513050626.14991-13-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190513050626.14991-1-vidyas@nvidia.com> References: <20190513050626.14991-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557724105; bh=kT0smlJh9/UaDrOm7DhIaB5W6ShxAfCAqe+hEk+M6tw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dOxtFC2Yy+4n/MlXH0JolSRukzOCUhnPIuleH/pmZybbYFjFc/tuCS+OyG+T5noM2 RE5uj24EsrVlfBj7wAeqXlG6WxeTNTFgUCc5GhfqRyU875OFByVoJqpaS65xnLpIu9 5kUujAmioQj+SipCF3t81jrpBO4Y2UfI9sDWeZyrDjLDOu7vmFUkANzV9BQAbAK9H2 SAdW6UWM+hlF89Qg148JGk+6Xnad65QxZVcHoVPHf8/6gTKyYq0FRfauSMWRrze+rB yqJtgTrhenbX1Xapbl7Lvio21DOdI8+bwyRJTY+AXYPklSMAg9xVb8cEC0UdnDAEz3 BdVCH2Wb0hJVQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe controller nodes to enable respective PCIe slots on P2972-0000 board. Following is the ownership of slots by different PCIe controllers. Controller-0 : M.2 Key-M slot Controller-1 : On-board Marvell eSATA controller Controller-3 : M.2 Key-E slot Signed-off-by: Vidya Sagar --- Changes since [v5]: * Arranged PCIe nodes in the order of their addresses Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed P2U label names to reflect new format that includes 'hsio'/'nvhs' strings to reflect UPHY brick they belong to Changes since [v1]: * Dropped 'pcie-' from phy-names property strings .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 0fd5bd29fbf9..30a83d4c5b69 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -191,7 +191,7 @@ regulator-boot-on; }; - sd3 { + vdd_1v8ao: sd3 { regulator-name = "VDD_1V8AO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 73801b48d1d8..a22704e76a84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -167,4 +167,45 @@ }; }; }; + + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_0>; + phy-names = "p2u-0"; + }; + + pcie@14140000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_7>; + phy-names = "p2u-0"; + }; + + pcie@14180000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, + <&p2u_hsio_5>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8ao>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; -- 2.17.1