From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Frank Rowand <frowand.list@gmail.com>,
Jingoo Han <jingoohan1@gmail.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-omap@vger.kernel.org>,
<linux-rockchip@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: [RFC PATCH 21/30] PCI: cadence: Add support to configure virtual functions
Date: Tue, 4 Jun 2019 18:45:07 +0530 [thread overview]
Message-ID: <20190604131516.13596-22-kishon@ti.com> (raw)
In-Reply-To: <20190604131516.13596-1-kishon@ti.com>
Now that support for SRIOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/pcie-cadence-ep.c | 104 ++++++++++++++++++++---
drivers/pci/controller/pcie-cadence.h | 5 ++
2 files changed, 98 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index df8fc495ffd9..3dc1a896c1e6 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -53,7 +53,18 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
struct pci_epf_header *hdr)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+ u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
struct cdns_pcie *pcie = &ep->pcie;
+ u32 reg;
+
+ if (vfn > 1) {
+ dev_dbg(&epc->dev, "Only Virtual Function #1 has deviceID\n");
+ return 0;
+ } else if (vfn == 1) {
+ reg = cap + PCI_SRIOV_VF_DID;
+ cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid);
+ return 0;
+ }
cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
@@ -84,11 +95,13 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
struct pci_epf_bar *epf_bar)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+ u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
struct cdns_pcie *pcie = &ep->pcie;
dma_addr_t bar_phys = epf_bar->phys_addr;
enum pci_barno bar = epf_bar->barno;
int flags = epf_bar->flags;
u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+ u32 first_vf_offset, stride;
u64 sz;
/* BAR size is 2^(aperture + 7) */
@@ -124,19 +137,38 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
addr0 = lower_32_bits(bar_phys);
addr1 = upper_32_bits(bar_phys);
+
+ if (vfn == 1) {
+ if (bar < BAR_4) {
+ reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn);
+ b = bar;
+ } else {
+ reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn);
+ b = bar - BAR_4;
+ }
+ } else {
+ if (bar < BAR_4) {
+ reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+ b = bar;
+ } else {
+ reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+ b = bar - BAR_4;
+ }
+ }
+
+ if (vfn > 0) {
+ first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap +
+ PCI_SRIOV_VF_OFFSET);
+ stride = cdns_pcie_ep_fn_readw(pcie, fn, cap +
+ PCI_SRIOV_VF_STRIDE);
+ fn = fn + first_vf_offset + ((vfn - 1) * stride);
+ }
+
cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
addr0);
cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
addr1);
- if (bar < BAR_4) {
- reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
- b = bar;
- } else {
- reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
- b = bar - BAR_4;
- }
-
cfg = cdns_pcie_readl(pcie, reg);
cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
@@ -179,8 +211,18 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
+ u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
+ u32 first_vf_offset, stride;
u32 r;
+ if (vfn > 0) {
+ first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap +
+ PCI_SRIOV_VF_OFFSET);
+ stride = cdns_pcie_ep_fn_readw(pcie, fn, cap +
+ PCI_SRIOV_VF_STRIDE);
+ fn = fn + first_vf_offset + ((vfn - 1) * stride);
+ }
+
r = find_first_zero_bit(&ep->ob_region_map,
sizeof(ep->ob_region_map) * BITS_PER_LONG);
if (r >= ep->max_regions - 1) {
@@ -220,9 +262,19 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
+ u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+ u32 first_vf_offset, stride;
u16 flags;
+ if (vfn > 0) {
+ first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_OFFSET);
+ stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_STRIDE);
+ fn = fn + first_vf_offset + ((vfn - 1) * stride);
+ }
+
/*
* Set the Multiple Message Capable bitfield into the Message Control
* register.
@@ -240,9 +292,19 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
+ u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+ u32 first_vf_offset, stride;
u16 flags, mme;
+ if (vfn > 0) {
+ first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_OFFSET);
+ stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_STRIDE);
+ fn = fn + first_vf_offset + ((vfn - 1) * stride);
+ }
+
/* Validate that the MSI feature is actually enabled. */
flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
if (!(flags & PCI_MSI_FLAGS_ENABLE))
@@ -257,7 +319,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
return mme;
}
-static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
+static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
u8 intx, bool is_asserted)
{
struct cdns_pcie *pcie = &ep->pcie;
@@ -320,10 +382,20 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
u8 interrupt_num)
{
struct cdns_pcie *pcie = &ep->pcie;
+ u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
u16 flags, mme, data, data_mask;
u8 msi_count;
u64 pci_addr, pci_addr_mask = 0xff;
+ u32 first_vf_offset, stride;
+
+ if (vfn > 0) {
+ first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_OFFSET);
+ stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap +
+ PCI_SRIOV_VF_STRIDE);
+ fn = fn + first_vf_offset + ((vfn - 1) * stride);
+ }
/* Check whether the MSI feature has been enabled by the PCI host. */
flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
@@ -364,7 +436,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
return 0;
}
-static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
+static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
enum pci_epc_irq_type type,
u16 interrupt_num)
{
@@ -414,10 +486,20 @@ static const struct pci_epc_features cdns_pcie_epc_features = {
.msix_capable = false,
};
+static const struct pci_epc_features cdns_pcie_epc_vf_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = true,
+ .align = 65536,
+};
+
static const struct pci_epc_features*
cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
{
- return &cdns_pcie_epc_features;
+ if (!vfunc_no)
+ return &cdns_pcie_epc_features;
+
+ return &cdns_pcie_epc_vf_features;
}
static const struct pci_epc_ops cdns_pcie_epc_ops = {
diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h
index 3cef398b50da..8237847bbc4e 100644
--- a/drivers/pci/controller/pcie-cadence.h
+++ b/drivers/pci/controller/pcie-cadence.h
@@ -50,6 +50,10 @@
(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \
+ (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \
+ (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008)
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
(GENMASK(4, 0) << ((b) * 8))
#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
@@ -99,6 +103,7 @@
#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
+#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200
/*
* Root Port Registers (PCI configuration space for the root port function)
--
2.17.1
next prev parent reply other threads:[~2019-06-04 13:19 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-04 13:14 [RFC PATCH 00/30] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 01/30] dt-bindings: PCI: cadence: Add DT binding to use PCIe with IOMMU Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 02/30] dt-bindings: PCI: cadence: Add binding to reset PERST# Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 03/30] dt-bindings: PCI: cadence: Update host DT bindings with TI specific compatible Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 04/30] dt-bindings: PCI: cadence: Update EP " Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 05/30] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 06/30] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 07/30] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 09/30] PCI: cadence: Add platform_data to start link and check link status Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 10/30] PCI: cadence: Use *_start_link() and *_wait_for_link() to establish link Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 11/30] PCI: cadence: Add support to drive PERST# line using GPIO Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 12/30] PCI: cadence: Make "mem" an optional memory resource Kishon Vijay Abraham I
2019-06-04 13:14 ` [RFC PATCH 13/30] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 14/30] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 15/30] PCI: endpoint: Replace spinlock with mutex Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 16/30] PCI: endpoint: Assign function number of each PF in EPC core Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 17/30] PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 18/30] PCI: endpoint: Add support to add virtual function in endpoint core Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 19/30] PCI: endpoint: Add support to link a physical function to a virtual function Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 20/30] PCI: endpoint: Add virtual function number in pci_epc ops Kishon Vijay Abraham I
2019-06-04 13:15 ` Kishon Vijay Abraham I [this message]
2019-06-04 13:15 ` [RFC PATCH 22/30] PCI: cadence: Configure pci_epc_features to align BAR addresses to 256 Bytes Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 23/30] of/platform: Export of_platform_device_create_pdata() Kishon Vijay Abraham I
2019-06-10 17:43 ` Rob Herring
2019-06-11 4:38 ` Kishon Vijay Abraham I
2019-07-19 10:55 ` Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 24/30] dt-bindings: PCI: J721E: Add DT bindings for PCIe controller in J721E Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 25/30] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 26/30] MAINTAINERS: Add MAINTAINER entry for PCIe on TI's J721E SoC Kishon Vijay Abraham I
2019-06-04 19:45 ` Bjorn Helgaas
2019-06-04 13:15 ` [RFC PATCH 27/30] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 28/30] misc: pci_endpoint_test: Avoid using module parameter to determine irqtype Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 29/30] misc: pci_endpoint_test: Populate sriov_configure ops to configure SRIOV device Kishon Vijay Abraham I
2019-06-04 13:15 ` [RFC PATCH 30/30] misc: pci_endpoint_test: Enable legacy interrupt Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190604131516.13596-22-kishon@ti.com \
--to=kishon@ti.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=tjoseph@cadence.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).