From: Thierry Reding <thierry.reding@gmail.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
jonathanh@nvidia.com, lorenzo.pieralisi@arm.com,
vidyas@nvidia.com, linux-tegra@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST#
Date: Tue, 4 Jun 2019 15:22:33 +0200 [thread overview]
Message-ID: <20190604132233.GT16519@ulmo> (raw)
In-Reply-To: <20190516055307.25737-28-mmaddireddy@nvidia.com>
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On Thu, May 16, 2019 at 11:23:06AM +0530, Manikanta Maddireddy wrote:
> Add support for GPIO based PERST# signal. GPIO number comes from per port
> PCIe device tree node.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V4: Using devm_gpiod_get_from_of_node() to get reset-gpios
>
> V3: Using helper function to get reset-gpios
>
> V2: Using standard "reset-gpio" property
>
> drivers/pci/controller/pci-tegra.c | 41 +++++++++++++++++++++++++-----
> 1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 06b99fcbf382..09b4d384ba38 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -17,6 +17,7 @@
> #include <linux/debugfs.h>
> #include <linux/delay.h>
> #include <linux/export.h>
> +#include <linux/gpio.h>
> #include <linux/interrupt.h>
> #include <linux/iopoll.h>
> #include <linux/irq.h>
> @@ -400,6 +401,8 @@ struct tegra_pcie_port {
> unsigned int lanes;
>
> struct phy **phys;
> +
> + struct gpio_desc *reset_gpiod;
Nit: I'd leave away the "d" at the end there. Or perhaps even the _gpio
suffix entirely. But it's fine either way.
> };
>
> struct tegra_pcie_bus {
> @@ -583,15 +586,23 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
> unsigned long value;
>
> /* pulse reset signal */
> - value = afi_readl(port->pcie, ctrl);
> - value &= ~AFI_PEX_CTRL_RST;
> - afi_writel(port->pcie, value, ctrl);
> + if (port->reset_gpiod) {
> + gpiod_set_value(port->reset_gpiod, 0);
So is this actually deasserting the reset pin, or is it asserting a
low-active reset? I think it's the latter, because ...
> + } else {
> + value = afi_readl(port->pcie, ctrl);
> + value &= ~AFI_PEX_CTRL_RST;
> + afi_writel(port->pcie, value, ctrl);
> + }
>
> usleep_range(1000, 2000);
>
> - value = afi_readl(port->pcie, ctrl);
> - value |= AFI_PEX_CTRL_RST;
> - afi_writel(port->pcie, value, ctrl);
> + if (port->reset_gpiod) {
> + gpiod_set_value(port->reset_gpiod, 1);
After this the port should be functional, right? I think it'd be better
to reverse the logic here and move the polarity of the GPIO into device
tree. gpiod_set_value() takes care of inverting the level internally if
the GPIO is marked as low-active in DT.
The end result is obviously the same, but it makes the usage much
clearer. If somebody want to write a DT for their board, they will look
at the schematics and see a low-active reset line and may be tempted to
describe it as such in DT, but with your current code that would be
exactly the wrong way around.
> + } else {
> + value = afi_readl(port->pcie, ctrl);
> + value |= AFI_PEX_CTRL_RST;
> + afi_writel(port->pcie, value, ctrl);
> + }
> }
>
> static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
> @@ -2238,6 +2249,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
> struct tegra_pcie_port *rp;
> unsigned int index;
> u32 value;
> + char *label;
>
> err = of_pci_get_devfn(port);
> if (err < 0) {
> @@ -2296,6 +2308,23 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
> if (IS_ERR(rp->base))
> return PTR_ERR(rp->base);
>
> + label = kasprintf(GFP_KERNEL, "pex-reset-%u", index);
devm_kasprintf()?
Thierry
> + if (!label) {
> + dev_err(dev, "failed to create reset GPIO label\n");
> + return -ENOMEM;
> + }
> +
> + rp->reset_gpiod = devm_gpiod_get_from_of_node(dev, port,
> + "reset-gpios", 0,
> + GPIOD_OUT_LOW,
> + label);
> + kfree(label);
> + if (IS_ERR(rp->reset_gpiod)) {
> + err = PTR_ERR(rp->reset_gpiod);
> + dev_err(dev, "failed to get reset GPIO: %d\n", err);
> + return err;
> + }
> +
> list_add_tail(&rp->list, &pcie->ports);
> }
>
> --
> 2.17.1
>
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next prev parent reply other threads:[~2019-06-04 13:22 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 5:52 [PATCH V4 00/28] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 01/28] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 02/28] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 03/28] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 04/28] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-06-04 13:08 ` Thierry Reding
2019-05-16 5:52 ` [PATCH V4 05/28] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 06/28] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 07/28] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 08/28] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 09/28] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 10/28] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 11/28] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 13/28] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 14/28] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 15/28] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 16/28] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 17/28] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 19/28] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-05-16 5:52 ` [PATCH V4 20/28] PCI: tegra: Use legacy IRQ for port service drivers Manikanta Maddireddy
2019-05-20 20:37 ` Bjorn Helgaas
2019-05-21 9:07 ` Manikanta Maddireddy
2019-05-16 5:53 ` [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-05-16 5:53 ` [PATCH V4 22/28] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-06-04 13:14 ` Thierry Reding
2019-06-04 14:10 ` Manikanta Maddireddy
2019-06-10 4:38 ` Manikanta Maddireddy
2019-06-13 14:39 ` Lorenzo Pieralisi
2019-06-13 15:42 ` Thierry Reding
2019-06-17 10:01 ` Manikanta Maddireddy
2019-06-17 11:47 ` Thierry Reding
2019-06-17 19:30 ` Bjorn Helgaas
2019-06-18 5:36 ` Manikanta Maddireddy
2019-06-18 10:49 ` Thierry Reding
2019-06-18 12:32 ` Johannes Berg
2019-06-18 13:40 ` Thierry Reding
2019-06-18 14:48 ` Johannes Berg
2019-06-19 13:38 ` Bjorn Helgaas
2019-06-19 13:40 ` Johannes Berg
2019-05-16 5:53 ` [PATCH V4 23/28] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-05-16 5:53 ` [PATCH V4 24/28] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-05-16 5:53 ` [PATCH V4 25/28] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-05-16 5:53 ` [PATCH V4 26/28] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-06-17 11:30 ` Thierry Reding
2019-06-17 11:38 ` Manikanta Maddireddy
2019-06-17 11:48 ` Thierry Reding
2019-05-16 5:53 ` [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-06-04 13:22 ` Thierry Reding [this message]
2019-06-13 15:24 ` Lorenzo Pieralisi
2019-06-14 10:37 ` Manikanta Maddireddy
2019-06-14 14:32 ` Lorenzo Pieralisi
2019-06-14 14:38 ` Manikanta Maddireddy
2019-06-14 14:50 ` Lorenzo Pieralisi
2019-06-14 14:56 ` Manikanta Maddireddy
2019-06-14 15:23 ` Thierry Reding
2019-06-14 15:59 ` Lorenzo Pieralisi
2019-06-14 16:30 ` Manikanta Maddireddy
2019-06-14 16:53 ` Lorenzo Pieralisi
2019-06-14 17:23 ` Manikanta Maddireddy
2019-06-17 9:48 ` Lorenzo Pieralisi
2019-06-17 10:27 ` Manikanta Maddireddy
2019-06-17 10:39 ` Lorenzo Pieralisi
2019-06-17 11:29 ` Thierry Reding
2019-06-17 11:26 ` Thierry Reding
2019-05-16 5:53 ` [PATCH V4 28/28] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
2019-06-04 13:22 ` Thierry Reding
2019-05-16 13:12 ` [PATCH V4 00/28] Enable Tegra PCIe root port features Bjorn Helgaas
2019-05-17 8:38 ` Manikanta Maddireddy
2019-06-10 4:45 ` Manikanta Maddireddy
2019-06-10 17:33 ` Lorenzo Pieralisi
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