From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V10 03/15] PCI: dwc: Perform dbi regs write lock towards the end
Date: Wed, 12 Jun 2019 15:23:27 +0530 [thread overview]
Message-ID: <20190612095339.20118-4-vidyas@nvidia.com> (raw)
In-Reply-To: <20190612095339.20118-1-vidyas@nvidia.com>
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence enabling write permission at
the start of function and disabling the same only towards the end.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* Moved write enable to the beginning of the API and write disable to the end
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* None
drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d3156446ff27 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 val, ctrl, num_ctrls;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ /*
+ * Enable DBI read-only registers for writing/updating configuration.
+ * Write permission gets disabled towards the end of this function.
+ */
+ dw_pcie_dbi_ro_wr_en(pci);
+
dw_pcie_setup(pci);
if (!pp->ops->msi_host_init) {
@@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
/* Setup interrupt pins */
- dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
val &= 0xffff00ff;
val |= 0x00000100;
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
- dw_pcie_dbi_ro_wr_dis(pci);
/* Setup bus numbers */
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
- /* Enable write permission for the DBI read-only register */
- dw_pcie_dbi_ro_wr_en(pci);
/* Program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
- /* Better disable write permission right after the update */
- dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
--
2.17.1
next prev parent reply other threads:[~2019-06-12 9:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-12 9:53 [PATCH V10 00/15] Add Tegra194 PCIe support Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 01/15] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 02/15] PCI: Disable MSI for Tegra194 root port Vidya Sagar
2019-06-12 9:53 ` Vidya Sagar [this message]
2019-06-18 6:34 ` [PATCH V10 03/15] PCI: dwc: Perform dbi regs write lock towards the end Jingoo Han
2019-06-12 9:53 ` [PATCH V10 04/15] PCI: dwc: Move config space capability search API Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 05/15] PCI: dwc: Add ext " Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 06/15] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 07/15] PCI: dwc: Add support to enable " Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 08/15] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 09/15] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-06-20 7:22 ` Kishon Vijay Abraham I
2019-06-12 9:53 ` [PATCH V10 11/15] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-06-20 10:55 ` Thierry Reding
2019-06-24 7:32 ` Vidya Sagar
2019-06-25 7:33 ` Thierry Reding
2019-06-12 9:53 ` [PATCH V10 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-06-20 11:01 ` Thierry Reding
2019-06-12 9:53 ` [PATCH V10 13/15] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-06-20 7:24 ` Kishon Vijay Abraham I
2019-06-20 23:23 ` Dmitry Osipenko
2019-06-22 17:56 ` Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 14/15] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-06-12 9:53 ` [PATCH V10 15/15] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-06-20 11:03 ` Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190612095339.20118-4-vidyas@nvidia.com \
--to=vidyas@nvidia.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=jonathanh@nvidia.com \
--cc=kishon@ti.com \
--cc=kthota@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=mperttunen@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sagar.tv@gmail.com \
--cc=thierry.reding@gmail.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).