From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1D95C31E57 for ; Mon, 17 Jun 2019 09:29:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 94C462084A for ; Mon, 17 Jun 2019 09:29:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728088AbfFQJ3G (ORCPT ); Mon, 17 Jun 2019 05:29:06 -0400 Received: from foss.arm.com ([217.140.110.172]:42972 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728036AbfFQJ3G (ORCPT ); Mon, 17 Jun 2019 05:29:06 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA6A1344; Mon, 17 Jun 2019 02:29:05 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E76ED3F246; Mon, 17 Jun 2019 02:29:03 -0700 (PDT) Date: Mon, 17 Jun 2019 10:29:01 +0100 From: Lorenzo Pieralisi To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Message-ID: <20190617092901.GB18020@e121166-lin.cambridge.arm.com> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> <20190612135400.GB15747@redmoon> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat, Jun 15, 2019 at 01:13:48AM +0000, Z.q. Hou wrote: > Hi Lorenzo, > > > -----Original Message----- > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com] > > Sent: 2019年6月12日 21:54 > > To: Z.q. Hou > > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > > l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li > > ; catalin.marinas@arm.com; will.deacon@arm.com; > > Mingkai Hu ; M.h. Lian ; > > Xiaowei Bao > > Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register > > accessors > > > > On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote: > > > From: Hou Zhiqiang > > > > > > There are some 8-bit and 16-bit registers in PCIe configuration space, > > > so add accessors for them. > > > > > > Signed-off-by: Hou Zhiqiang > > > Reviewed-by: Minghuan Lian > > > Reviewed-by: Subrahmanya Lingappa > > > --- > > > V5: > > > - Corrected and retouched the subject and changelog. > > > - No functionality change. > > > > > > drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++ > > > 1 file changed, 20 insertions(+) > > > > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > > > b/drivers/pci/controller/pcie-mobiveil.c > > > index 411e9779da12..456adfee393c 100644 > > > --- a/drivers/pci/controller/pcie-mobiveil.c > > > +++ b/drivers/pci/controller/pcie-mobiveil.c > > > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, > > u32 off) > > > return csr_read(pcie, off, 0x4); > > > } > > > > > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) { > > > + return csr_read(pcie, off, 0x2); > > > +} > > > + > > > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) { > > > + return csr_read(pcie, off, 0x1); > > > +} > > > + > > > static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > > > { > > > csr_write(pcie, val, off, 0x4); > > > } > > > > > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > > > +{ > > > + csr_write(pcie, val, off, 0x2); > > > +} > > > + > > > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > > > +{ > > > + csr_write(pcie, val, off, 0x1); > > > +} > > > + > > > > They are not used so you should drop this patch. > > NXP Layerscape PCIe Gen4 controller driver will use them, so don't > drop it. You add functions when they are needed, so drop this patch and squash it to the patch that use these functions. Lorenzo > Thanks, > Zhiqiang > > > > > Lorenzo > > > > > static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) { > > > return (csr_readl(pcie, LTSSM_STATUS) & > > > -- > > > 2.17.1 > > >