From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A336C31E5B for ; Mon, 17 Jun 2019 17:40:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 556CA2084D for ; Mon, 17 Jun 2019 17:40:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="imLFIwus" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726047AbfFQRkh (ORCPT ); Mon, 17 Jun 2019 13:40:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:11900 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725995AbfFQRkh (ORCPT ); Mon, 17 Jun 2019 13:40:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 17 Jun 2019 10:40:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 17 Jun 2019 10:40:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 17 Jun 2019 10:40:36 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 17 Jun 2019 17:40:36 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 17 Jun 2019 17:40:36 +0000 Received: from manikanta-bm2.nvidia.com (10.124.1.5) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 17 Jun 2019 17:40:32 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V5 11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Date: Mon, 17 Jun 2019 23:09:36 +0530 Message-ID: <20190617173952.29363-12-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617173952.29363-1-mmaddireddy@nvidia.com> References: <20190617173952.29363-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560793236; bh=lnH4gJH/7dzxtBG8dWZhlgPrMwptCAVf625YQMUKGf0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=imLFIwus0kHH2KKwCunuXDP1zy36VoSrYcOlvLUbzMHG9P3w7A89F6ydSQaDQ9R5k btRlIQnNrqMPDIe4XXwfF4EIWQv52hVoGftu4fAVWldaltXBXvSZ9VHX9B+pfEMKla UuZdHlNBGXbuucQ7FSBNoZM1lmrA/uKq/Yt8MrITVkNwJ1Fv8JV9oS8r/VJ/6jb1iq 3PB2OPMWi8Z4Sy6KY4VdJ+ROGO+1TitYSoaEO5lO8bp0TYsC/4K6/xm9leGwgV0g0B fPRRJHIJv0a8qg1jUmPE6WENS7HIOhovu0br66z6RQ6vdnmyaTFCOnLF7px76dqji5 +z9T7vjLLEFSQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PM message are truncated while entering L1 or L2, which is resulting in receiver errors. Set the required bit to finish processing DLLP before link enter L1 or L2. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V5: No change V4: No change V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index ca02866fbbb4..7cd2a8948919 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -212,6 +212,9 @@ #define RP_VEND_CTL1 0x00000f48 #define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_XP_BIST 0x00000f4c +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -538,6 +541,14 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value |= RP_VEND_XP_OPPORTUNISTIC_ACK; value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; writel(value, port->base + RP_VEND_XP); + + /* + * LTSSM will wait for DLLP to finish before entering L1 or L2, + * to avoid truncation of PM messages which results in receiver errors + */ + value = readl(port->base + RP_VEND_XP_BIST); + value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(value, port->base + RP_VEND_XP_BIST); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) -- 2.17.1