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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: thierry.reding@gmail.com, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com,
	vidyas@nvidia.com, linux-tegra@vger.kernel.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V6 18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20
Date: Thu, 20 Jun 2019 17:26:38 +0100
Message-ID: <20190620162638.GA18771@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <20190618180206.4908-19-mmaddireddy@nvidia.com>

On Tue, Jun 18, 2019 at 11:31:57PM +0530, Manikanta Maddireddy wrote:
> Cacheable upstream transactions are supported in Tegra20 and Tegra186 only.
> AFI_CACHE* registers are available in Tegra20 to support cacheable upstream
> transactions. In Tegra186, AFI_AXCACHE register is defined instead of
> AFI_CACHE* to be in line with its MSS design. Therefore, program AFI_CACHE*

What's an MSS ?

Lorenzo

> registers only for Tegra20.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> ---
> V6: No change
> 
> V5: No change
> 
> V4: No change
> 
> V3: Initialized has_cache_bars variable for each soc data structure.
> 
> V2: Used soc variable for comparision instead of compatible string.
> 
>  drivers/pci/controller/pci-tegra.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 3d9028cecc18..a746d963ca36 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -323,6 +323,7 @@ struct tegra_pcie_soc {
>  	bool program_deskew_time;
>  	bool raw_violation_fixup;
>  	bool update_fc_timer;
> +	bool has_cache_bars;
>  	struct {
>  		struct {
>  			u32 rp_ectl_2_r1;
> @@ -932,11 +933,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
>  	afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
>  	afi_writel(pcie, 0, AFI_FPCI_BAR5);
>  
> -	/* map all upstream transactions as uncached */
> -	afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
> -	afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
> +	if (pcie->soc->has_cache_bars) {
> +		/* map all upstream transactions as uncached */
> +		afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
> +		afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
> +	}
>  
>  	/* MSI translations are setup only when needed */
>  	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
> @@ -2441,6 +2444,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>  	.program_deskew_time = false,
>  	.raw_violation_fixup = false,
>  	.update_fc_timer = false,
> +	.has_cache_bars = true,
>  	.ectl.enable = false,
>  };
>  
> @@ -2469,6 +2473,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
>  	.program_deskew_time = false,
>  	.raw_violation_fixup = false,
>  	.update_fc_timer = false,
> +	.has_cache_bars = false,
>  	.ectl.enable = false,
>  };
>  
> @@ -2492,6 +2497,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>  	.program_deskew_time = false,
>  	.raw_violation_fixup = true,
>  	.update_fc_timer = false,
> +	.has_cache_bars = false,
>  	.ectl.enable = false,
>  };
>  
> @@ -2515,6 +2521,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
>  	.program_deskew_time = true,
>  	.raw_violation_fixup = false,
>  	.update_fc_timer = true,
> +	.has_cache_bars = false,
>  	.ectl = {
>  		.regs = {
>  			.rp_ectl_2_r1 = 0x0000000f,
> @@ -2555,6 +2562,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>  	.program_deskew_time = false,
>  	.raw_violation_fixup = false,
>  	.update_fc_timer = false,
> +	.has_cache_bars = false,
>  	.ectl.enable = false,
>  };
>  
> -- 
> 2.17.1
> 

  reply index

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18 18:01 [PATCH V6 00/27] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 01/27] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 02/27] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 03/27] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 04/27] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-06-20 14:27   ` Lorenzo Pieralisi
2019-06-20 14:46     ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 05/27] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 06/27] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-06-20 14:32   ` Lorenzo Pieralisi
2019-06-20 14:57     ` Manikanta Maddireddy
2019-06-20 15:22       ` Lorenzo Pieralisi
2019-06-18 18:01 ` [PATCH V6 07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 08/27] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 09/27] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 10/27] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 11/27] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 12/27] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 13/27] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 14/27] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 15/27] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 16/27] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 17/27] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 18/27] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-06-20 16:26   ` Lorenzo Pieralisi [this message]
2019-06-20 16:35     ` Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 19/27] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-06-18 18:01 ` [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port Manikanta Maddireddy
2019-06-18 19:48   ` Bjorn Helgaas
2019-06-19  3:55     ` Manikanta Maddireddy
2019-06-19  9:50       ` Lorenzo Pieralisi
2019-06-18 18:02 ` [PATCH V6 21/27] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 22/27] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 23/27] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-06-20 10:14   ` Thierry Reding
2019-06-18 18:02 ` [PATCH V6 24/27] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 25/27] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-06-18 18:02 ` [PATCH V6 26/27] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-07-04 14:48   ` Jon Hunter
2019-07-04 15:29     ` Manikanta Maddireddy
2019-07-04 17:23       ` Jon Hunter
2019-06-18 18:02 ` [PATCH V6 27/27] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
2019-06-20 10:25 ` [PATCH V6 00/27] Enable Tegra PCIe root port features Thierry Reding
2019-06-20 10:53   ` Lorenzo Pieralisi
2019-06-20 11:14     ` Thierry Reding
2019-06-20 16:46 ` Lorenzo Pieralisi
2019-06-20 17:23   ` Manikanta Maddireddy

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