From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Minghuan Lian <Minghuan.Lian@nxp.com>,
Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>,
Sasha Levin <sashal@kernel.org>,
linux-pci@vger.kernel.org
Subject: [PATCH AUTOSEL 4.19 067/101] PCI: mobiveil: Fix the Class Code field
Date: Fri, 19 Jul 2019 00:06:58 -0400 [thread overview]
Message-ID: <20190719040732.17285-67-sashal@kernel.org> (raw)
In-Reply-To: <20190719040732.17285-1-sashal@kernel.org>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[ Upstream commit 0122af0a08243f344a438f924e5c2486486555b3 ]
Fix up the Class Code field in PCI configuration space and set it to
PCI_CLASS_BRIDGE_PCI.
Move the Class Code fixup to function mobiveil_host_init() where
it belongs.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pci/controller/pcie-mobiveil.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
index d9f2d0f2d602..3e81e68b5ce0 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -565,6 +565,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
}
}
+ /* fixup for PCIe class register */
+ value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
+ value &= 0xff;
+ value |= (PCI_CLASS_BRIDGE_PCI << 16);
+ csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+
/* setup MSI hardware registers */
mobiveil_pcie_enable_msi(pcie);
@@ -805,9 +811,6 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
goto error;
}
- /* fixup for PCIe class register */
- csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
-
/* initialize the IRQ domains */
ret = mobiveil_pcie_init_irq_domain(pcie);
if (ret) {
--
2.20.1
next prev parent reply other threads:[~2019-07-19 4:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190719040732.17285-1-sashal@kernel.org>
2019-07-19 4:06 ` [PATCH AUTOSEL 4.19 016/101] PCI: Return error if cannot probe VF Sasha Levin
2019-07-19 4:06 ` [PATCH AUTOSEL 4.19 041/101] PCI: sysfs: Ignore lockdep for remove attribute Sasha Levin
2019-07-19 4:06 ` [PATCH AUTOSEL 4.19 046/101] PCI: xilinx-nwl: Fix Multi MSI data programming Sasha Levin
2019-07-19 4:06 ` [PATCH AUTOSEL 4.19 065/101] PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30 Sasha Levin
2019-07-19 4:06 ` [PATCH AUTOSEL 4.19 066/101] PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows Sasha Levin
2019-07-19 4:06 ` Sasha Levin [this message]
2019-07-19 4:07 ` [PATCH AUTOSEL 4.19 069/101] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Sasha Levin
2019-07-19 4:07 ` [PATCH AUTOSEL 4.19 070/101] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Sasha Levin
2019-07-19 4:07 ` [PATCH AUTOSEL 4.19 078/101] PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB Sasha Levin
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