From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A219C433FF for ; Wed, 7 Aug 2019 23:01:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FC7D2171F for ; Wed, 7 Aug 2019 23:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565218915; bh=880CjrWqcw/b0n8e8loUwkiYFlbtOJVJsxG1uGHV1Ps=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=V0ofGQ9cW0WXC/ct9phDuoguyeonW09uEcdYFi09UmedJK/wFfmu/gdDbvcCo/c7E qL2mHQGj9+M+wltsh3OS4HlCxW0AQuf7I68fhU+Z+hDjXr7z05NDOYaX6M3CdftwD7 GGYrdV97cLabkHyyHNj28w12ddnYPoC1fFqLFGcU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730302AbfHGXBy (ORCPT ); Wed, 7 Aug 2019 19:01:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:39576 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729960AbfHGXBy (ORCPT ); Wed, 7 Aug 2019 19:01:54 -0400 Received: from localhost (unknown [69.71.4.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0B4882171F; Wed, 7 Aug 2019 23:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1565218913; bh=880CjrWqcw/b0n8e8loUwkiYFlbtOJVJsxG1uGHV1Ps=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=BbLvpPEMmpazhnJCMsxKGQMri/b6UwTY2G01eANjdrk1kgPgQjO5BcVdhwrMtdD8Q ZqpwBCoCCS3SkcIdXzMH9Sk8xyumGYznOE02Oaq9WTjmtRmkG6n2jHH4feWHLT9Vie YPBkPOIdMFQ79/+nv6Zs9xYpheC8VcJcyAN7zlnw= Date: Wed, 7 Aug 2019 18:01:49 -0500 From: Bjorn Helgaas To: Sumit Saxena Cc: Christian.Koenig@amd.com, linux-pci@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH V2] PCI: set BAR size bits correctly in Resize BAR control register Message-ID: <20190807230149.GA151852@google.com> References: <20190725192552.24295-1-sumit.saxena@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190725192552.24295-1-sumit.saxena@broadcom.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Jul 26, 2019 at 12:55:52AM +0530, Sumit Saxena wrote: > In Resize BAR control register, bits[8:12] represents size of BAR. > As per PCIe specification, below is encoded values in register bits > to actual BAR size table: > > Bits BAR size > 0 1 MB > 1 2 MB > 2 4 MB > 3 8 MB > -- > > For 1 MB BAR size, BAR size bits should be set to 0 but incorrectly > these bits are set to "1f". Latest megaraid_sas and mpt3sas adapters > which support Resizable BAR with 1 MB BAR size fails to initialize > during system resume from S3 sleep. > > Fix: Correctly calculate BAR size bits for Resize BAR control register. > > V2: > -Simplified calculation of BAR size bits as suggested by Christian Koenig. > > CC: stable@vger.kernel.org # v4.16+ > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203939 > Fixes: d3252ace0bc652a1a244455556b6a549f969bf99 ("PCI: Restore resized BAR state on resume") > Signed-off-by: Sumit Saxena > --- > drivers/pci/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 29ed5ec1ac27..e59921296125 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -1438,7 +1438,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev) > pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); > bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; > res = pdev->resource + bar_idx; > - size = order_base_2((resource_size(res) >> 20) | 1) - 1; > + size = order_base_2(resource_size(res) >> 20); Since BAR sizes are always powers of 2, wouldn't this be simpler as: size = ilog2(resource_size(res)) - 20; which nicely matches the table in PCIe r5.0, sec 7.8.6.3? > ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; > ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; > pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); > -- > 2.18.1 >