From: Bjorn Helgaas <helgaas@kernel.org>
To: "Koenig, Christian" <Christian.Koenig@amd.com>
Cc: Sumit Saxena <sumit.saxena@broadcom.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH V2] PCI: set BAR size bits correctly in Resize BAR control register
Date: Thu, 8 Aug 2019 07:31:24 -0500 [thread overview]
Message-ID: <20190808123124.GD151852@google.com> (raw)
In-Reply-To: <ed70bffc-eed8-c3c5-ee9b-22e1cad1ae06@amd.com>
On Thu, Aug 08, 2019 at 07:01:03AM +0000, Koenig, Christian wrote:
> Am 08.08.19 um 01:01 schrieb Bjorn Helgaas:
> > On Fri, Jul 26, 2019 at 12:55:52AM +0530, Sumit Saxena wrote:
> >> In Resize BAR control register, bits[8:12] represents size of BAR.
> >> As per PCIe specification, below is encoded values in register bits
> >> to actual BAR size table:
> >>
> >> Bits BAR size
> >> 0 1 MB
> >> 1 2 MB
> >> 2 4 MB
> >> 3 8 MB
> >> --
> >>
> >> For 1 MB BAR size, BAR size bits should be set to 0 but incorrectly
> >> these bits are set to "1f". Latest megaraid_sas and mpt3sas adapters
> >> which support Resizable BAR with 1 MB BAR size fails to initialize
> >> during system resume from S3 sleep.
> >>
> >> Fix: Correctly calculate BAR size bits for Resize BAR control register.
> >>
> >> V2:
> >> -Simplified calculation of BAR size bits as suggested by Christian Koenig.
> >>
> >> CC: stable@vger.kernel.org # v4.16+
> >> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203939
> >> Fixes: d3252ace0bc652a1a244455556b6a549f969bf99 ("PCI: Restore resized BAR state on resume")
> >> Signed-off-by: Sumit Saxena <sumit.saxena@broadcom.com>
> >> ---
> >> drivers/pci/pci.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> >> index 29ed5ec1ac27..e59921296125 100644
> >> --- a/drivers/pci/pci.c
> >> +++ b/drivers/pci/pci.c
> >> @@ -1438,7 +1438,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
> >> pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
> >> bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
> >> res = pdev->resource + bar_idx;
> >> - size = order_base_2((resource_size(res) >> 20) | 1) - 1;
> >> + size = order_base_2(resource_size(res) >> 20);
> > Since BAR sizes are always powers of 2, wouldn't this be simpler as:
> >
> > size = ilog2(resource_size(res)) - 20;
> >
> > which nicely matches the table in PCIe r5.0, sec 7.8.6.3?
>
> Yeah, that should obviously work as well.
>
> We would have a serious problem in the resource management if the
> resource size is smaller than 1MB or not a power of two.
Yes, definitely. Resizable BARs are required by spec to be 1MB or
larger, but this does niggle at me a little bit, too. It probably
saves a few bits in pci_dev to recompute this at restore-time, but
honestly, I think it would be more obviously correct to just do the
simple-minded thing of saving and restoring the entire register.
> Feel free to add my r-b.
Done, thanks!
> Regards,
> Christian.
>
> >
> >> ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
> >> ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
> >> pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
> >> --
> >> 2.18.1
> >>
>
next prev parent reply other threads:[~2019-08-08 12:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-25 19:25 [PATCH V2] PCI: set BAR size bits correctly in Resize BAR control register Sumit Saxena
2019-07-25 11:58 ` Koenig, Christian
2019-08-07 23:01 ` Bjorn Helgaas
2019-08-08 7:01 ` Koenig, Christian
2019-08-08 12:31 ` Bjorn Helgaas [this message]
2019-08-07 23:17 ` Bjorn Helgaas
2019-08-07 23:27 ` Bjorn Helgaas
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