From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <digetx@gmail.com>, <mperttunen@nvidia.com>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V15 02/13] PCI: Disable MSI for Tegra root ports
Date: Fri, 9 Aug 2019 10:15:58 +0530 [thread overview]
Message-ID: <20190809044609.20401-3-vidyas@nvidia.com> (raw)
In-Reply-To: <20190809044609.20401-1-vidyas@nvidia.com>
Tegra PCIe rootports don't generate MSI interrupts for PME and AER events.
Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports
service drivers registering their respective ISRs with MSI interrupt and
to let only INTx be used for all events.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* Included older Tegra chips to extend the quirk as this issue is present in
older Tegra chips as well.
V10:
* None
V9:
* None
V8:
* Changed quirk macro to consider class code as well to avoid this quirk
getting applied to Tegra194 when it is operating in endpoint mode. Also
quoted relevant sections from PCIe spec in comments.
V7:
* This is a new patch
drivers/pci/quirks.c | 53 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 208aacf39329..168782c5d23b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2592,6 +2592,59 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_NVENET_15,
nvenet_msi_disable);
+/*
+ * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
+ * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
+ * generate MSI interrupts for PME and AER events instead only INTx interrupts
+ * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
+ * for other events, since PCIe specificiation doesn't support using a mix of
+ * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
+ * service drivers registering their respective ISRs for MSIs.
+ */
+static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
+{
+ dev->no_msi = 1;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+
/*
* Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
* config register. This register controls the routing of legacy
--
2.17.1
next prev parent reply other threads:[~2019-08-09 4:46 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 4:45 [PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-09 4:45 ` [PATCH V15 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-08-09 4:45 ` Vidya Sagar [this message]
2019-08-09 4:45 ` [PATCH V15 03/13] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 04/13] PCI: dwc: Move config space capability search API Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 05/13] PCI: dwc: Add ext " Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 08/13] PCI: dwc: Add support to enable " Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 09/13] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-08-09 4:46 ` [PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-08-12 10:23 ` Thierry Reding
2019-08-09 4:46 ` [PATCH V15 13/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-13 10:57 ` Lorenzo Pieralisi
2019-08-13 11:36 ` Vidya Sagar
2019-08-12 10:25 ` [PATCH V15 00/13] " Thierry Reding
2019-08-12 10:29 ` Vidya Sagar
2019-08-12 10:34 ` Thierry Reding
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