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Fri, 13 Sep 2019 14:54:32 +0000 From: Jason Gunthorpe To: Megha Dey CC: "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "linux-pci@vger.kernel.org" , "maz@kernel.org" , "bhelgaas@google.com" , "rafael@kernel.org" , "gregkh@linuxfoundation.org" , "tglx@linutronix.de" , "hpa@zytor.com" , "alex.williamson@redhat.com" , "ashok.raj@intel.com" , "megha.dey@intel.com" , "jacob.jun.pan@intel.com" , Jacob Pan , Sanjay Kumar Subject: Re: [RFC V1 5/7] x86/ims: Introduce x86_ims_ops Thread-Topic: [RFC V1 5/7] x86/ims: Introduce x86_ims_ops Thread-Index: AQHVadCkfyl/W5/j50OrxTgjCXPOsacpsqWA Date: Fri, 13 Sep 2019 14:54:32 +0000 Message-ID: <20190913145427.GD5310@mellanox.com> References: <1568338328-22458-1-git-send-email-megha.dey@linux.intel.com> <1568338328-22458-6-git-send-email-megha.dey@linux.intel.com> In-Reply-To: <1568338328-22458-6-git-send-email-megha.dey@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: YQXPR01CA0118.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:c00:41::47) To VI1PR05MB4141.eurprd05.prod.outlook.com (2603:10a6:803:4d::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=jgg@mellanox.com; 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received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: nQdEHbx/93CWOyxkFq6iVl1dhLgEcBJ800n8x96B4C7IbyhqkydOF5wrppu9GG6ibvj2VRQeMlF/4raxfphLPuYr5eqBoF7yw7WhUu/edjeP+CbiGLePY9d+bWgR7X4tN7c/f/WEUnnENhVm1TmbqPStmGkvlWXQZY+7Wz6Gcq9x0prqCrFVdaQjwsZTag+P6ZYv+j5SipbKV7gablOpNqIVTZziNSBMbANlqYy98pJcfB6h/MEiueEaOkXSuQctp1m8VKrFedzWGtLngvF4ETCXTX57sQcAADJr46hgX8Ysm1dP1elhUnXJf28a0UCtZ5smfXIZqBCK+8UFYFva3lqfaKA6ZXjnTqHSrUBmODYPEpCSxkU/DXIxBVucT7QAbTH4YnJ6CNw5VUzzlMmmzw95OmnqPUNBRSa2wlw1gx4= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-ID: <02143F9BCF3490478FA6A227D9649F62@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: cec94c82-bb23-4696-944c-08d7385a4936 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Sep 2019 14:54:32.4079 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ED0cfn+7M6sgw2IvzfmiyFYWTJ4OASyw9/RwbWyByDOGQLp4DxbFjwerX8Q5WDcJRRHexMf9+F5dsXbYuZgBcQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR05MB4448 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Sep 12, 2019 at 06:32:06PM -0700, Megha Dey wrote: > This patch introduces an x86 specific indirect mechanism to setup the > interrupt message storage. The IMS specific functions (setup, teardown, > restore) become function pointers in an x86_ims_ops struct, that > defaults to their implementations in ims.c and ims-msi.c. >=20 > Cc: Jacob Pan > Signed-off-by: Sanjay Kumar > Signed-off-by: Megha Dey > arch/x86/include/asm/pci.h | 4 ++++ > arch/x86/include/asm/x86_init.h | 10 ++++++++++ > arch/x86/kernel/apic/ims.c | 18 ++++++++++++++++++ > arch/x86/kernel/x86_init.c | 23 +++++++++++++++++++++++ > drivers/base/ims-msi.c | 34 ++++++++++++++++++++++++++++++++++ > include/linux/msi.h | 6 ++++++ > 6 files changed, 95 insertions(+) >=20 > diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h > index e662f98..2ef513f 100644 > +++ b/arch/x86/include/asm/pci.h > @@ -114,6 +114,10 @@ struct msi_desc; > int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); > void native_teardown_msi_irq(unsigned int irq); > void native_restore_msi_irqs(struct pci_dev *dev); > +#ifdef CONFIG_MSI_IMS > +int native_setup_ims_irqs(struct device *dev, int nvec); > +#endif > + > #else > #define native_setup_msi_irqs NULL > #define native_teardown_msi_irq NULL > diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_i= nit.h > index ac09341..9c2cbbb 100644 > +++ b/arch/x86/include/asm/x86_init.h > @@ -287,6 +287,15 @@ struct x86_msi_ops { > void (*restore_msi_irqs)(struct pci_dev *dev); > }; > =20 > +struct device; > + > +struct x86_ims_ops { > + int (*setup_ims_irqs)(struct device *dev, int nvec); > + void (*teardown_ims_irq)(unsigned int irq); > + void (*teardown_ims_irqs)(struct device *dev); > + void (*restore_ims_irqs)(struct device *dev); > +}; This looks alot like the generic struct msi_controller.. Jason