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From: Daniel Drake <drake@endlessm.com>
To: rafael@kernel.org, bhelgaas@google.com
Cc: mathias.nyman@linux.intel.com, linux@endlessm.com,
	linux-pm@vger.kernel.org, linux-pci@vger.kernel.org
Subject: [PATCH] PCI: also apply D3 delay when leaving D3cold
Date: Fri, 27 Sep 2019 17:02:02 +0800	[thread overview]
Message-ID: <20190927090202.1468-1-drake@endlessm.com> (raw)

This delay is needed to fix resume from s2idle of the XHCI controller on
AMD Ryzen SoCs, where a 20ms delay is required (this will be quirked
in a followup patch), to avoid this failure:

  xhci_hcd 0000:03:00.4: WARN: xHC restore state timeout
  xhci_hcd 0000:03:00.4: PCI post-resume error -110!

The D3 delay is already being performed in a runtime resume from D3cold,
through the following sequence of events:

     pci_pm_runtime_resume
  -> pci_restore_standard_config
  -> pci_set_power_state(D0)
  -> __pci_start_power_transition
  -> pci_platform_power_transition
  -> pci_update_current_state

At this point, the device has been set to D0 at the platform level,
so pci_update_current_state() reads pmcsr and updates dev->current_state
to D3hot. Now when we reach pci_raw_set_power_state() the D3 delay will
be applied.

However, the D3cold resume from s2idle path is somewhat different, and
we arrive at the same function without hitting pci_update_current_state()
along the way:
     pci_pm_resume_noirq
  -> pci_pm_default_resume_early
  -> pci_power_up
  -> pci_raw_set_power_state

As dev->current_state is D3cold, the D3 delay is skipped and the XHCI
controllers fail to be powered up.

Apply the D3 delay in the s2idle resume case too, in order to fix
USB functionality after resume.

Link: http://lkml.kernel.org/r/CAD8Lp47Vh69gQjROYG69=waJgL7hs1PwnLonL9+27S_TcRhixA@mail.gmail.com
Signed-off-by: Daniel Drake <drake@endlessm.com>
---
 drivers/pci/pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e7982af9a5d8..ab15fa5eda2c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -883,7 +883,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
 	 * Mandatory power management transition delays; see PCI PM 1.1
 	 * 5.6.1 table 18
 	 */
-	if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
+	if (state == PCI_D3hot || dev->current_state == PCI_D3hot
+			|| dev->current_state == PCI_D3cold)
 		pci_dev_d3_sleep(dev);
 	else if (state == PCI_D2 || dev->current_state == PCI_D2)
 		udelay(PCI_PM_D2_DELAY);
-- 
2.20.1


             reply	other threads:[~2019-09-27  9:02 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-27  9:02 Daniel Drake [this message]
2019-10-11 10:14 ` Rafael J. Wysocki
2019-10-14  6:18   ` Daniel Drake
2019-10-14  9:22     ` Rafael J. Wysocki
2019-10-14  9:46       ` Daniel Drake
2019-10-14 10:40         ` Rafael J. Wysocki
2019-10-14 10:51         ` [PATCH] PCI: PM: Consolidate runtime resume and system resume paths Rafael J. Wysocki
2019-10-14 11:20           ` Rafael J. Wysocki
2019-10-14 11:25           ` [PATCH] PCI: PM: Fix pci_power_up() Rafael J. Wysocki
2019-10-15  5:10             ` Daniel Drake
2019-10-15  8:20               ` Rafael J. Wysocki
2019-10-15 19:20             ` Bjorn Helgaas
2019-10-15 21:19               ` Rafael J. Wysocki

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