From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09B1CC32792 for ; Mon, 30 Sep 2019 14:39:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DBD8C21927 for ; Mon, 30 Sep 2019 14:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730809AbfI3Ojs (ORCPT ); Mon, 30 Sep 2019 10:39:48 -0400 Received: from foss.arm.com ([217.140.110.172]:55898 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730780AbfI3Ojs (ORCPT ); Mon, 30 Sep 2019 10:39:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ACB0428; Mon, 30 Sep 2019 07:39:47 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A963B3F706; Mon, 30 Sep 2019 07:39:46 -0700 (PDT) Date: Mon, 30 Sep 2019 15:39:41 +0100 From: Lorenzo Pieralisi To: Grzegorz Jaszczyk Cc: Thomas Petazzoni , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcin Wojtas , Russell King - ARM Linux Subject: Re: [PATCH v2] PCI: aardvark: fix big endian support Message-ID: <20190930143941.GA3744@e121166-lin.cambridge.arm.com> References: <1563279127-30678-1-git-send-email-jaz@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Mon, Sep 30, 2019 at 10:17:33AM +0200, Grzegorz Jaszczyk wrote: > Hello, > > I want to kindly remind about this patch. I need Thomas' ACK on these patches to merge them. Thanks, Lorenzo > Best regards, > Grzegorz > > wt., 16 lip 2019 o 14:12 Grzegorz Jaszczyk napisał(a): > > > > Initialise every not-byte wide fields of emulated pci bridge config > > space with proper cpu_to_le* macro. This is required since the structure > > describing config space of emulated bridge assumes little-endian > > convention. > > > > Signed-off-by: Grzegorz Jaszczyk > > --- > > v1->v2 > > - add missing cpu_to_le32 for class_revison assignment (issues found by > > Thomas Petazzoni and also detected by Sparse tool). > > > > drivers/pci/controller/pci-aardvark.c | 12 +++++++----- > > 1 file changed, 7 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > > index 134e030..178e92f 100644 > > --- a/drivers/pci/controller/pci-aardvark.c > > +++ b/drivers/pci/controller/pci-aardvark.c > > @@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie) > > { > > struct pci_bridge_emul *bridge = &pcie->bridge; > > > > - bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff; > > - bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16; > > + bridge->conf.vendor = > > + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); > > + bridge->conf.device = > > + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); > > bridge->conf.class_revision = > > - advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff; > > + cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); > > > > /* Support 32 bits I/O addressing */ > > bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; > > bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; > > > > /* Support 64 bits memory pref */ > > - bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64; > > - bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64; > > + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); > > + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); > > > > /* Support interrupt A for MSI feature */ > > bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; > > -- > > 2.7.4 > >