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From: Thomas Petazzoni <>
To: Remi Pommarel <>
Cc: Lorenzo Pieralisi <>,
	Bjorn Helgaas <>,
	Ellie Reeves <>,,,
Subject: Re: [PATCH v2] PCI: aardvark: Wait for endpoint to be ready before training link
Date: Mon, 14 Oct 2019 21:29:38 +0200	[thread overview]
Message-ID: <20191014212938.14516102@windsurf.home> (raw)
In-Reply-To: <>

Hello Remi,

On Wed, 22 May 2019 23:33:50 +0200
Remi Pommarel <> wrote:

> When configuring pcie reset pin from gpio (e.g. initially set by
> u-boot) to pcie function this pin goes low for a brief moment
> asserting the PERST# signal. Thus connected device enters fundamental
> reset process and link configuration can only begin after a minimal
> 100ms delay (see [1]).
> Because the pin configuration comes from the "default" pinctrl it is
> implicitly configured before the probe callback is called:
> driver_probe_device()
>   really_probe()
>     ...
>     pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset
>                            function and PERST# is asserted */
>     ...
>     drv->probe()
> [1] "PCI Express Base Specification", REV. 4.0
>     PCI Express, February 19 2014, 6.6.1 Conventional Reset
> Signed-off-by: Remi Pommarel <>

It is always a bit annoying to add another 100ms in the boot path, but
I don't see an easy alternative solution, so:

Acked-by: Thomas Petazzoni <>

Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering

  parent reply	other threads:[~2019-10-14 19:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-22 21:33 [PATCH v2] PCI: aardvark: Wait for endpoint to be ready before training link Remi Pommarel
2019-08-06 18:49 ` Remi Pommarel
2019-10-14 15:39   ` Lorenzo Pieralisi
2019-10-14 19:29 ` Thomas Petazzoni [this message]
2019-10-15  9:53 ` Lorenzo Pieralisi

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