* [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe @ 2019-11-02 0:27 Bjorn Andersson 2019-11-02 0:27 ` [PATCH v2 1/2] dt-bindings: " Bjorn Andersson ` (2 more replies) 0 siblings, 3 replies; 7+ messages in thread From: Bjorn Andersson @ 2019-11-02 0:27 UTC (permalink / raw) To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel This second iteration of the patch series fixes review comments on v1 and has been tested with both PCIe controllers found on the Qualcomm SDM845. Bjorn Andersson (2): dt-bindings: PCI: qcom: Add support for SDM845 PCIe PCI: qcom: Add support for SDM845 PCIe controller .../devicetree/bindings/pci/qcom,pcie.txt | 19 +++ drivers/pci/controller/dwc/pcie-qcom.c | 152 ++++++++++++++++++ 2 files changed, 171 insertions(+) -- 2.23.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/2] dt-bindings: PCI: qcom: Add support for SDM845 PCIe 2019-11-02 0:27 [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson @ 2019-11-02 0:27 ` Bjorn Andersson 2019-11-05 22:42 ` Rob Herring 2019-11-02 0:27 ` [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson 2019-11-03 8:24 ` [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Vinod Koul 2 siblings, 1 reply; 7+ messages in thread From: Bjorn Andersson @ 2019-11-02 0:27 UTC (permalink / raw) To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel Add compatible and necessary clocks and resets definitions for the SDM845 PCIe controller. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changes since v1: - Split out binding in separate patch .../devicetree/bindings/pci/qcom,pcie.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index ada80b01bf0c..981b4de12807 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -11,6 +11,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sdm845" for sdm845 - reg: Usage: required @@ -126,6 +127,18 @@ - "master_bus" AXI Master clock - "slave_bus" AXI Slave clock +-clock-names: + Usage: required for sdm845 + Value type: <stringlist> + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "pipe" PIPE clock + - resets: Usage: required Value type: <prop-encoded-array> @@ -188,6 +201,12 @@ - "pwr" PWR reset - "ahb" AHB reset +- reset-names: + Usage: required for sdm845 + Value type: <stringlist> + Definition: Should contain the following entries + - "pci" PCIe core reset + - power-domains: Usage: required for apq8084 and msm8996/apq8096 Value type: <prop-encoded-array> -- 2.23.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Add support for SDM845 PCIe 2019-11-02 0:27 ` [PATCH v2 1/2] dt-bindings: " Bjorn Andersson @ 2019-11-05 22:42 ` Rob Herring 0 siblings, 0 replies; 7+ messages in thread From: Rob Herring @ 2019-11-05 22:42 UTC (permalink / raw) To: Bjorn Andersson Cc: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel On Fri, 1 Nov 2019 17:27:20 -0700, Bjorn Andersson wrote: > Add compatible and necessary clocks and resets definitions for the > SDM845 PCIe controller. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes since v1: > - Split out binding in separate patch > > .../devicetree/bindings/pci/qcom,pcie.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller 2019-11-02 0:27 [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson 2019-11-02 0:27 ` [PATCH v2 1/2] dt-bindings: " Bjorn Andersson @ 2019-11-02 0:27 ` Bjorn Andersson 2019-11-04 9:41 ` Philipp Zabel 2019-11-03 8:24 ` [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Vinod Koul 2 siblings, 1 reply; 7+ messages in thread From: Bjorn Andersson @ 2019-11-02 0:27 UTC (permalink / raw) To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel The SDM845 has one Gen2 and one Gen3 controller, add support for these. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changes since v1: - Style changes requested by Stan - Tested with second PCIe controller as well drivers/pci/controller/dwc/pcie-qcom.c | 152 +++++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7e581748ee9f..35f4980480bb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -54,6 +54,7 @@ #define PCIE20_PARF_LTSSM 0x1B0 #define PCIE20_PARF_SID_OFFSET 0x234 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C +#define PCIE20_PARF_DEVICE_TYPE 0x1000 #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -80,6 +81,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define DEVICE_TYPE_RC 0x4 + #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; @@ -139,12 +142,20 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +struct qcom_pcie_resources_2_7_0 { + struct clk_bulk_data clks[6]; + struct regulator_bulk_data supplies[2]; + struct reset_control *pci_reset; + struct clk *pipe_clk; +}; + union qcom_pcie_resources { struct qcom_pcie_resources_1_0_0 v1_0_0; struct qcom_pcie_resources_2_1_0 v2_1_0; struct qcom_pcie_resources_2_3_2 v2_3_2; struct qcom_pcie_resources_2_3_3 v2_3_3; struct qcom_pcie_resources_2_4_0 v2_4_0; + struct qcom_pcie_resources_2_7_0 v2_7_0; }; struct qcom_pcie; @@ -1068,6 +1079,136 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) return ret; } +static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + int ret; + + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); + if (IS_ERR(res->pci_reset)) + return PTR_ERR(res->pci_reset); + + res->supplies[0].supply = "vdda"; + res->supplies[1].supply = "vddpe-3v3"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), + res->supplies); + if (ret) + return ret; + + res->clks[0].id = "aux"; + res->clks[1].id = "cfg"; + res->clks[2].id = "bus_master"; + res->clks[3].id = "bus_slave"; + res->clks[4].id = "slave_q2a"; + res->clks[5].id = "tbu"; + + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; + + res->pipe_clk = devm_clk_get(dev, "pipe"); + return PTR_ERR_OR_ZERO(res->pipe_clk); +} + +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + u32 val; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); + if (ret < 0) { + dev_err(dev, "cannot enable regulators\n"); + return ret; + } + + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + goto err_disable_regulators; + + ret = reset_control_assert(res->pci_reset); + if (ret < 0) { + dev_err(dev, "cannot deassert pci reset\n"); + goto err_disable_clocks; + } + + msleep(20); + + ret = reset_control_deassert(res->pci_reset); + if (ret < 0) { + dev_err(dev, "cannot deassert pci reset\n"); + goto err_assert_resets; + } + + ret = clk_prepare_enable(res->pipe_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable pipe clock\n"); + goto err_assert_resets; + } + + /* configure PCIe to RC mode */ + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* change DBI base address */ + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val &= ~BIT(29); + writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + + val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val |= BIT(4); + writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + val |= BIT(31); + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + } + + return 0; +err_assert_resets: + reset_control_assert(res->pci_reset); +err_disable_clocks: + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; +} + +static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); +} + +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + return clk_prepare_enable(res->pipe_clk); +} + +static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + clk_disable_unprepare(res->pipe_clk); +} + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); @@ -1167,6 +1308,16 @@ static const struct qcom_pcie_ops ops_2_3_3 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ +static const struct qcom_pcie_ops ops_2_7_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, }; @@ -1282,6 +1433,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, + { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, { } }; -- 2.23.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller 2019-11-02 0:27 ` [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson @ 2019-11-04 9:41 ` Philipp Zabel 2019-11-06 20:56 ` Bjorn Andersson 0 siblings, 1 reply; 7+ messages in thread From: Philipp Zabel @ 2019-11-04 9:41 UTC (permalink / raw) To: Bjorn Andersson, Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel Hi Bjorn, On Fri, 2019-11-01 at 17:27 -0700, Bjorn Andersson wrote: > The SDM845 has one Gen2 and one Gen3 controller, add support for these. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes since v1: > - Style changes requested by Stan > - Tested with second PCIe controller as well > > drivers/pci/controller/dwc/pcie-qcom.c | 152 +++++++++++++++++++++++++ > 1 file changed, 152 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 7e581748ee9f..35f4980480bb 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -54,6 +54,7 @@ [...] > +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > +{ > + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > + struct dw_pcie *pci = pcie->pci; > + struct device *dev = pci->dev; > + u32 val; > + int ret; > + > + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > + if (ret < 0) { > + dev_err(dev, "cannot enable regulators\n"); > + return ret; > + } > + > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > + if (ret < 0) > + goto err_disable_regulators; > + > + ret = reset_control_assert(res->pci_reset); > + if (ret < 0) { > + dev_err(dev, "cannot deassert pci reset\n"); > + goto err_disable_clocks; > + } If for any of the above fails, the reset line is left in its default state, presumably unasserted. Is there a reason to assert and keep it asserted if enabling the clocks fails below? > + msleep(20); > + > + ret = reset_control_deassert(res->pci_reset); > + if (ret < 0) { > + dev_err(dev, "cannot deassert pci reset\n"); > + goto err_assert_resets; Nitpick: this seems superfluous since the reset line was just asserted 20 ms before. Maybe just: goto err_disable_clocks; > + } > + > + ret = clk_prepare_enable(res->pipe_clk); > + if (ret) { > + dev_err(dev, "cannot prepare/enable pipe clock\n"); > + goto err_assert_resets; > + } > + > + /* configure PCIe to RC mode */ > + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); > + > + /* enable PCIe clocks and resets */ > + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > + val &= ~BIT(0); > + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > + > + /* change DBI base address */ > + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); > + > + /* MAC PHY_POWERDOWN MUX DISABLE */ > + val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); > + val &= ~BIT(29); > + writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); > + > + val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > + val |= BIT(4); > + writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > + > + if (IS_ENABLED(CONFIG_PCI_MSI)) { > + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + val |= BIT(31); > + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + } > + > + return 0; > +err_assert_resets: > + reset_control_assert(res->pci_reset); So maybe this can just be removed. The reset isn't asserted in deinit either. regards Philipp ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller 2019-11-04 9:41 ` Philipp Zabel @ 2019-11-06 20:56 ` Bjorn Andersson 0 siblings, 0 replies; 7+ messages in thread From: Bjorn Andersson @ 2019-11-06 20:56 UTC (permalink / raw) To: Philipp Zabel Cc: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel On Mon 04 Nov 01:41 PST 2019, Philipp Zabel wrote: > Hi Bjorn, > > On Fri, 2019-11-01 at 17:27 -0700, Bjorn Andersson wrote: > > The SDM845 has one Gen2 and one Gen3 controller, add support for these. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > > > Changes since v1: > > - Style changes requested by Stan > > - Tested with second PCIe controller as well > > > > drivers/pci/controller/dwc/pcie-qcom.c | 152 +++++++++++++++++++++++++ > > 1 file changed, 152 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > > index 7e581748ee9f..35f4980480bb 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > @@ -54,6 +54,7 @@ > [...] > > +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > > +{ > > + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > > + struct dw_pcie *pci = pcie->pci; > > + struct device *dev = pci->dev; > > + u32 val; > > + int ret; > > + > > + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > > + if (ret < 0) { > > + dev_err(dev, "cannot enable regulators\n"); > > + return ret; > > + } > > + > > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > > + if (ret < 0) > > + goto err_disable_regulators; > > + > > + ret = reset_control_assert(res->pci_reset); > > + if (ret < 0) { > > + dev_err(dev, "cannot deassert pci reset\n"); > > + goto err_disable_clocks; > > + } > > If for any of the above fails, the reset line is left in its default > state, presumably unasserted. Is there a reason to assert and keep it > asserted if enabling the clocks fails below? > No, I don't think there's any reason for doing this and looking at the downstream driver, they don't even propagate this error. > > + msleep(20); And I see now that downstream has this as 1ms, will update and retest again. > > + > > + ret = reset_control_deassert(res->pci_reset); > > + if (ret < 0) { > > + dev_err(dev, "cannot deassert pci reset\n"); > > + goto err_assert_resets; > > Nitpick: this seems superfluous since the reset line was just asserted > 20 ms before. Maybe just: > > goto err_disable_clocks; Yes, this seems reasonable. > > > + } > > + > > + ret = clk_prepare_enable(res->pipe_clk); > > + if (ret) { > > + dev_err(dev, "cannot prepare/enable pipe clock\n"); > > + goto err_assert_resets; > > + } > > + > > + /* configure PCIe to RC mode */ > > + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); > > + > > + /* enable PCIe clocks and resets */ > > + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > > + val &= ~BIT(0); > > + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > > + > > + /* change DBI base address */ > > + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); > > + > > + /* MAC PHY_POWERDOWN MUX DISABLE */ > > + val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); > > + val &= ~BIT(29); > > + writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); > > + > > + val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + val |= BIT(4); > > + writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + > > + if (IS_ENABLED(CONFIG_PCI_MSI)) { > > + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > > + val |= BIT(31); > > + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > > + } > > + > > + return 0; > > +err_assert_resets: > > + reset_control_assert(res->pci_reset); > > So maybe this can just be removed. The reset isn't asserted in deinit > either. > Sounds good. Thanks for your review, Philipp! Regards, Bjorn ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe 2019-11-02 0:27 [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson 2019-11-02 0:27 ` [PATCH v2 1/2] dt-bindings: " Bjorn Andersson 2019-11-02 0:27 ` [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson @ 2019-11-03 8:24 ` Vinod Koul 2 siblings, 0 replies; 7+ messages in thread From: Vinod Koul @ 2019-11-03 8:24 UTC (permalink / raw) To: Bjorn Andersson Cc: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, Rob Herring, Mark Rutland, linux-arm-msm, linux-pci, devicetree, linux-kernel On 01-11-19, 17:27, Bjorn Andersson wrote: > This second iteration of the patch series fixes review comments on v1 and has > been tested with both PCIe controllers found on the Qualcomm SDM845. Reviewed-by: Vinod Koul <vkoul@kernel.org> -- ~Vinod ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-06 20:56 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-11-02 0:27 [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson 2019-11-02 0:27 ` [PATCH v2 1/2] dt-bindings: " Bjorn Andersson 2019-11-05 22:42 ` Rob Herring 2019-11-02 0:27 ` [PATCH v2 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson 2019-11-04 9:41 ` Philipp Zabel 2019-11-06 20:56 ` Bjorn Andersson 2019-11-03 8:24 ` [PATCH v2 0/2] PCI: qcom: Add support for SDM845 PCIe Vinod Koul
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