From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC42FC5DF60 for ; Thu, 7 Nov 2019 14:03:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A1A85222C2 for ; Thu, 7 Nov 2019 14:03:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728180AbfKGODE (ORCPT ); Thu, 7 Nov 2019 09:03:04 -0500 Received: from mga05.intel.com ([192.55.52.43]:31664 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726754AbfKGODD (ORCPT ); Thu, 7 Nov 2019 09:03:03 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 06:03:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,278,1569308400"; d="scan'208";a="213028106" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.163]) by fmsmga001.fm.intel.com with SMTP; 07 Nov 2019 06:03:00 -0800 Received: by lahna (sSMTP sendmail emulation); Thu, 07 Nov 2019 16:02:59 +0200 Date: Thu, 7 Nov 2019 16:02:59 +0200 From: Mika Westerberg To: Bjorn Helgaas Cc: "Rafael J. Wysocki" , Len Brown , Valerio Passini , linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, Benjamin Herrenschmidt Subject: Re: [PATCH] ACPI / hotplug / PCI: Allocate resources directly under the non-hotplug bridge Message-ID: <20191107140259.GN2552@lahna.fi.intel.com> References: <20191107090333.GG2552@lahna.fi.intel.com> <20191107135246.GA90684@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191107135246.GA90684@google.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Nov 07, 2019 at 07:52:46AM -0600, Bjorn Helgaas wrote: > > > What would happen if a device below one of the non-hotplug bridges, > > > e.g., 3a:00.0, had an I/O BAR? Would this patch still work? > > > > I think it would still work because now we call pci_bus_size_bridges() > > only for non-hotplug bridge which do not have I/O window open so > > pbus_size_io() fails to find the "free" I/O resource on that bus and the > > kernel then fails to assign that I/O resource for the device. > > Not sure I understand; are you saying that we wouldn't have the EC/GPE > issue, but we'd be unable to use a device below 3a:00.0 that happened > to have an I/O BAR? Yes. > That doesn't sound optimal because there is I/O space available that > could be routed to 3a:00.0 If the none of the upstream bridges up to the PCIe root port does not have I/O window open, I don't think we can do much about it. Unless I'm missing something of course.