From: Rob Herring <robh@kernel.org>
To: Dilip Kota <eswara.kota@linux.intel.com>
Cc: gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
andriy.shevchenko@intel.com, cheol.yong.kim@intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v5 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Date: Tue, 12 Nov 2019 13:17:27 -0600 [thread overview]
Message-ID: <20191112191727.GA31422@bogus> (raw)
In-Reply-To: <73655e49e80ac08826ad2d470e1387ba1b662d83.1572950559.git.eswara.kota@linux.intel.com>
On Wed, Nov 06, 2019 at 11:44:01AM +0800, Dilip Kota wrote:
> Add YAML schemas for PCIe RC controller on Intel Gateway SoCs
> which is Synopsys DesignWare based PCIe core.
>
> Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> ---
> Changes on v5:
> Add Reviewed-by Andrew Murray.
> Add possible values and default value for max-link-speed.
> Remove $ref and add maximum and default for reset-assert-ms.
> Set true flag for linux,pci-domain.
> Define maxItems for ranges and clock.
> Define maximum for num-lanes.
> Update required list:
> Add #address-cells, #size-cells, #interrupt-cells.
> Remove num-lanes and linux,pci-domain.
> Add required header files in example.
> Remove status entry in example.
>
> changes on v4:
> Add "snps,dw-pcie" compatible.
> Rename phy-names property value to pcie.
> And maximum and minimum values to num-lanes.
> Add ref for reset-assert-ms entry and update the
> description for easy understanding.
> Remove PCIe core interrupt entry.
>
> changes on v3:
> Add the appropriate License-Identifier
> Rename intel,rst-interval to 'reset-assert-us'
> Add additionalProperties: false
> Rename phy-names to 'pciephy'
> Remove the dtsi node split of SoC and board in the example
> Add #interrupt-cells = <1>; or else interrupt parsing will fail
> Name yaml file with compatible name
>
> .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++
> 1 file changed, 138 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
I'm working on a common PCI schema which will shrink this, but in the
meantime:
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2019-11-12 19:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-06 3:44 [PATCH v5 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-11-06 3:44 ` [PATCH v5 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-11-12 19:17 ` Rob Herring [this message]
2019-11-13 2:39 ` Dilip Kota
2019-11-06 3:44 ` [PATCH v5 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-11-06 12:24 ` Andy Shevchenko
2019-11-11 8:08 ` Dilip Kota
2019-11-12 7:18 ` Dilip Kota
2019-11-08 10:42 ` Andrew Murray
2019-11-11 8:09 ` Dilip Kota
2019-11-06 3:44 ` [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper function Dilip Kota
2019-11-06 9:43 ` Gustavo Pimentel
2019-11-11 6:24 ` Dilip Kota
2019-11-07 21:03 ` Jingoo Han
2019-11-08 10:43 ` Andrew Murray
2019-11-11 8:10 ` Dilip Kota
2019-11-11 8:09 ` Dilip Kota
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