From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
<rjw@rjwysocki.net>, <lenb@kernel.org>, <andrew.murray@arm.com>,
<treding@nvidia.com>, <jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V3 1/2] arm64: tegra: Re-order PCIe aperture mappings to support ACPI boot
Date: Sat, 11 Jan 2020 00:44:59 +0530
Message-ID: <20200110191500.9538-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20200110191500.9538-1-vidyas@nvidia.com>
Re-order Tegra194's PCIe aperture mappings to have IO window moved to
64-bit aperture and have the entire 32-bit aperture used for accessing
the configuration space. This makes it to use the entire 32MB of the 32-bit
aperture for ECAM purpose while booting through ACPI.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* New change in this series
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++++++++++------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ccac43be12ac..5d790ec5bdef 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1247,9 +1247,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ ranges = <0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
+ 0x82000000 0x00 0x40000000 0x12 0x30000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
pcie@14120000 {
@@ -1292,9 +1292,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ ranges = <0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
+ 0x82000000 0x00 0x40000000 0x12 0x70000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
pcie@14140000 {
@@ -1337,9 +1337,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
- 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ ranges = <0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
+ 0x82000000 0x00 0x40000000 0x12 0xb0000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
pcie@14160000 {
@@ -1382,9 +1382,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ ranges = <0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
+ 0x82000000 0x00 0x40000000 0x17 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
pcie@14180000 {
@@ -1427,9 +1427,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ ranges = <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
+ 0x82000000 0x00 0x40000000 0x1b 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
pcie@141a0000 {
@@ -1476,9 +1476,9 @@
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
- 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ ranges = <0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
+ 0x82000000 0x00 0x40000000 0x1f 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
+ 0x81000000 0x00 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
};
sysram@40000000 {
--
2.17.1
next prev parent reply index
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 17:49 [PATCH] PCI: Add MCFG quirks for Tegra194 host controllers Vidya Sagar
2020-01-03 18:04 ` Bjorn Helgaas
2020-01-04 3:44 ` Vidya Sagar
2020-01-17 12:17 ` Lorenzo Pieralisi
2020-01-20 11:10 ` Thierry Reding
2020-01-20 15:18 ` Lorenzo Pieralisi
2020-01-21 13:44 ` Thierry Reding
2020-01-23 10:49 ` Lorenzo Pieralisi
2020-02-06 16:46 ` Thierry Reding
2020-02-07 14:50 ` Bjorn Helgaas
2020-02-07 16:51 ` Thierry Reding
2020-02-07 18:34 ` Bjorn Helgaas
2020-01-04 21:53 ` kbuild test robot
2020-01-06 8:27 ` [PATCH V2] " Vidya Sagar
2020-01-10 19:14 ` [PATCH V3 0/2] " Vidya Sagar
2020-01-10 19:14 ` Vidya Sagar [this message]
2020-01-10 19:15 ` [PATCH V3 2/2] " Vidya Sagar
2020-01-17 11:42 ` Thierry Reding
2020-01-16 17:18 ` [PATCH V3 0/2] " Vidya Sagar
Reply instructions:
You may reply publically to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200110191500.9538-2-vidyas@nvidia.com \
--to=vidyas@nvidia.com \
--cc=andrew.murray@arm.com \
--cc=bhelgaas@google.com \
--cc=jonathanh@nvidia.com \
--cc=kthota@nvidia.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=rjw@rjwysocki.net \
--cc=sagar.tv@gmail.com \
--cc=treding@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Linux-PCI Archive on lore.kernel.org
Archives are clonable:
git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git
# If you have public-inbox 1.1+ installed, you may
# initialize and index your mirror using the following commands:
public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
linux-pci@vger.kernel.org
public-inbox-index linux-pci
Example config snippet for mirrors
Newsgroup available over NNTP:
nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git