From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-acpi@vger.kernel.org, devicetree@vger.kernel.org,
iommu@lists.linux-foundation.org, will@kernel.org
Cc: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,
lorenzo.pieralisi@arm.com, guohanjun@huawei.com,
sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,
robin.murphy@arm.com, bhelgaas@google.com, eric.auger@redhat.com,
jonathan.cameron@huawei.com, zhangfei.gao@linaro.org
Subject: [PATCH v5 06/13] iommu/arm-smmu-v3: Add context descriptor tables allocators
Date: Wed, 15 Jan 2020 13:52:32 +0100 [thread overview]
Message-ID: <20200115125239.136759-7-jean-philippe@linaro.org> (raw)
In-Reply-To: <20200115125239.136759-1-jean-philippe@linaro.org>
Support for SSID will require allocating context descriptor tables. Move
the context descriptor allocation to separate functions.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
drivers/iommu/arm-smmu-v3.c | 47 +++++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index e7c7e34d385f..a3438e256bd0 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -563,11 +563,13 @@ struct arm_smmu_ctx_desc {
struct arm_smmu_ctx_desc_cfg {
__le64 *cdtab;
dma_addr_t cdtab_dma;
+ unsigned int num_l1_ents;
};
struct arm_smmu_s1_cfg {
struct arm_smmu_ctx_desc_cfg cdcfg;
struct arm_smmu_ctx_desc cd;
+ u8 s1cdmax;
};
struct arm_smmu_s2_cfg {
@@ -1502,6 +1504,35 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
cdptr[3] = cpu_to_le64(cfg->cd.mair);
}
+static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain)
+{
+ size_t l1size;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+ struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
+ struct arm_smmu_ctx_desc_cfg *cdcfg = &cfg->cdcfg;
+
+ cdcfg->num_l1_ents = 1UL << cfg->s1cdmax;
+ l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
+ cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma,
+ GFP_KERNEL);
+ if (!cdcfg->cdtab) {
+ dev_warn(smmu->dev, "failed to allocate context descriptor\n");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
+{
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
+ struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg;
+ size_t l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
+
+ dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma);
+ cdcfg->cdtab_dma = 0;
+ cdcfg->cdtab = NULL;
+}
+
/* Stream table manipulation functions */
static void
arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
@@ -2145,11 +2176,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
if (cfg->cdcfg.cdtab) {
- dmam_free_coherent(smmu_domain->smmu->dev,
- CTXDESC_CD_DWORDS << 3,
- cfg->cdcfg.cdtab,
- cfg->cdcfg.cdtab_dma);
-
+ arm_smmu_free_cd_tables(smmu_domain);
arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);
}
} else {
@@ -2173,15 +2200,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
if (asid < 0)
return asid;
- cfg->cdcfg.cdtab = dmam_alloc_coherent(smmu->dev,
- CTXDESC_CD_DWORDS << 3,
- &cfg->cdcfg.cdtab_dma,
- GFP_KERNEL);
- if (!cfg->cdcfg.cdtab) {
- dev_warn(smmu->dev, "failed to allocate context descriptor\n");
- ret = -ENOMEM;
+ ret = arm_smmu_alloc_cd_tables(smmu_domain);
+ if (ret)
goto out_free_asid;
- }
cfg->cd.asid = (u16)asid;
cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
--
2.24.1
next prev parent reply other threads:[~2020-01-15 12:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-15 12:52 [PATCH v5 00/13] iommu: Add PASID support to Arm SMMUv3 Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 01/13] iommu/arm-smmu-v3: Drop __GFP_ZERO flag from DMA allocation Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 02/13] dt-bindings: document PASID property for IOMMU masters Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 03/13] iommu/arm-smmu-v3: Parse PASID devicetree property of platform devices Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 04/13] ACPI/IORT: Parse SSID property of named component node Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 05/13] iommu/arm-smmu-v3: Prepare arm_smmu_s1_cfg for SSID support Jean-Philippe Brucker
2020-01-15 12:52 ` Jean-Philippe Brucker [this message]
2020-01-15 12:52 ` [PATCH v5 07/13] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 08/13] iommu/arm-smmu-v3: Propagate ssid_bits Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 09/13] iommu/arm-smmu-v3: Prepare for handling arm_smmu_write_ctx_desc() failure Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 10/13] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 11/13] iommu/arm-smmu-v3: Improve add_device() error handling Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 12/13] PCI/ATS: Add PASID stubs Jean-Philippe Brucker
2020-01-15 12:52 ` [PATCH v5 13/13] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker
2020-01-15 16:42 ` [PATCH v5 00/13] iommu: Add PASID support to Arm SMMUv3 Will Deacon
2020-01-15 18:29 ` Jean-Philippe Brucker
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