From: Remi Pommarel <repk@triplefau.lt>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Yue Wang <yue.wang@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v6 7/7] PCI: amlogic: Use AXG PCIE
Date: Fri, 24 Jan 2020 09:35:29 +0100 [thread overview]
Message-ID: <20200124083529.GX1803@voidbox> (raw)
In-Reply-To: <20200123232943.10229-8-repk@triplefau.lt>
Add missing Reviewed/Acked-by from v5
On Fri, Jan 24, 2020 at 12:29:43AM +0100, Remi Pommarel wrote:
> Now that PCIE PHY has been introduced for AXG, the whole has_shared_phy
> logic can be mutualized between AXG and G12A platforms.
>
> This new PHY makes use of the shared MIPI/PCIE analog PHY found on AXG
> platforms, which need to be used in order to have reliable PCIE
> communications.
>
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> ---
> drivers/pci/controller/dwc/pci-meson.c | 116 +++++--------------------
> 1 file changed, 22 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
> index 3772b02a5c55..3715dceca1bf 100644
> --- a/drivers/pci/controller/dwc/pci-meson.c
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -66,7 +66,6 @@
> #define PORT_CLK_RATE 100000000UL
> #define MAX_PAYLOAD_SIZE 256
> #define MAX_READ_REQ_SIZE 256
> -#define MESON_PCIE_PHY_POWERUP 0x1c
> #define PCIE_RESET_DELAY 500
> #define PCIE_SHARED_RESET 1
> #define PCIE_NORMAL_RESET 0
> @@ -81,26 +80,19 @@ enum pcie_data_rate {
> struct meson_pcie_mem_res {
> void __iomem *elbi_base;
> void __iomem *cfg_base;
> - void __iomem *phy_base;
> };
>
> struct meson_pcie_clk_res {
> struct clk *clk;
> - struct clk *mipi_gate;
> struct clk *port_clk;
> struct clk *general_clk;
> };
>
> struct meson_pcie_rc_reset {
> - struct reset_control *phy;
> struct reset_control *port;
> struct reset_control *apb;
> };
>
> -struct meson_pcie_param {
> - bool has_shared_phy;
> -};
> -
> struct meson_pcie {
> struct dw_pcie pci;
> struct meson_pcie_mem_res mem_res;
> @@ -108,7 +100,6 @@ struct meson_pcie {
> struct meson_pcie_rc_reset mrst;
> struct gpio_desc *reset_gpio;
> struct phy *phy;
> - const struct meson_pcie_param *param;
> };
>
> static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
> @@ -130,13 +121,6 @@ static int meson_pcie_get_resets(struct meson_pcie *mp)
> {
> struct meson_pcie_rc_reset *mrst = &mp->mrst;
>
> - if (!mp->param->has_shared_phy) {
> - mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
> - if (IS_ERR(mrst->phy))
> - return PTR_ERR(mrst->phy);
> - reset_control_deassert(mrst->phy);
> - }
> -
> mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
> if (IS_ERR(mrst->port))
> return PTR_ERR(mrst->port);
> @@ -162,22 +146,6 @@ static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
> return devm_ioremap_resource(dev, res);
> }
>
> -static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
> - struct meson_pcie *mp,
> - const char *id)
> -{
> - struct device *dev = mp->pci.dev;
> - struct resource *res;
> -
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
> - if (!res) {
> - dev_err(dev, "No REG resource %s\n", id);
> - return ERR_PTR(-ENXIO);
> - }
> -
> - return devm_ioremap(dev, res->start, resource_size(res));
> -}
> -
> static int meson_pcie_get_mems(struct platform_device *pdev,
> struct meson_pcie *mp)
> {
> @@ -189,14 +157,6 @@ static int meson_pcie_get_mems(struct platform_device *pdev,
> if (IS_ERR(mp->mem_res.cfg_base))
> return PTR_ERR(mp->mem_res.cfg_base);
>
> - /* Meson AXG SoC has two PCI controllers use same phy register */
> - if (!mp->param->has_shared_phy) {
> - mp->mem_res.phy_base =
> - meson_pcie_get_mem_shared(pdev, mp, "phy");
> - if (IS_ERR(mp->mem_res.phy_base))
> - return PTR_ERR(mp->mem_res.phy_base);
> - }
> -
> return 0;
> }
>
> @@ -204,37 +164,33 @@ static int meson_pcie_power_on(struct meson_pcie *mp)
> {
> int ret = 0;
>
> - if (mp->param->has_shared_phy) {
> - ret = phy_init(mp->phy);
> - if (ret)
> - return ret;
> + ret = phy_init(mp->phy);
> + if (ret)
> + return ret;
>
> - ret = phy_power_on(mp->phy);
> - if (ret) {
> - phy_exit(mp->phy);
> - return ret;
> - }
> - } else
> - writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
> + ret = phy_power_on(mp->phy);
> + if (ret) {
> + phy_exit(mp->phy);
> + return ret;
> + }
>
> return 0;
> }
>
> +static void meson_pcie_power_off(struct meson_pcie *mp)
> +{
> + phy_power_off(mp->phy);
> + phy_exit(mp->phy);
> +}
> +
> static int meson_pcie_reset(struct meson_pcie *mp)
> {
> struct meson_pcie_rc_reset *mrst = &mp->mrst;
> int ret = 0;
>
> - if (mp->param->has_shared_phy) {
> - ret = phy_reset(mp->phy);
> - if (ret)
> - return ret;
> - } else {
> - reset_control_assert(mrst->phy);
> - udelay(PCIE_RESET_DELAY);
> - reset_control_deassert(mrst->phy);
> - udelay(PCIE_RESET_DELAY);
> - }
> + ret = phy_reset(mp->phy);
> + if (ret)
> + return ret;
>
> reset_control_assert(mrst->port);
> reset_control_assert(mrst->apb);
> @@ -286,12 +242,6 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp)
> if (IS_ERR(res->port_clk))
> return PTR_ERR(res->port_clk);
>
> - if (!mp->param->has_shared_phy) {
> - res->mipi_gate = meson_pcie_probe_clock(dev, "mipi", 0);
> - if (IS_ERR(res->mipi_gate))
> - return PTR_ERR(res->mipi_gate);
> - }
> -
> res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
> if (IS_ERR(res->general_clk))
> return PTR_ERR(res->general_clk);
> @@ -562,7 +512,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>
> static int meson_pcie_probe(struct platform_device *pdev)
> {
> - const struct meson_pcie_param *match_data;
> struct device *dev = &pdev->dev;
> struct dw_pcie *pci;
> struct meson_pcie *mp;
> @@ -576,17 +525,10 @@ static int meson_pcie_probe(struct platform_device *pdev)
> pci->dev = dev;
> pci->ops = &dw_pcie_ops;
>
> - match_data = of_device_get_match_data(dev);
> - if (!match_data) {
> - dev_err(dev, "failed to get match data\n");
> - return -ENODEV;
> - }
> - mp->param = match_data;
> -
> - if (mp->param->has_shared_phy) {
> - mp->phy = devm_phy_get(dev, "pcie");
> - if (IS_ERR(mp->phy))
> - return PTR_ERR(mp->phy);
> + mp->phy = devm_phy_get(dev, "pcie");
> + if (IS_ERR(mp->phy)) {
> + dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
> + return PTR_ERR(mp->phy);
> }
>
> mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> @@ -636,30 +578,16 @@ static int meson_pcie_probe(struct platform_device *pdev)
> return 0;
>
> err_phy:
> - if (mp->param->has_shared_phy) {
> - phy_power_off(mp->phy);
> - phy_exit(mp->phy);
> - }
> -
> + meson_pcie_power_off(mp);
> return ret;
> }
>
> -static struct meson_pcie_param meson_pcie_axg_param = {
> - .has_shared_phy = false,
> -};
> -
> -static struct meson_pcie_param meson_pcie_g12a_param = {
> - .has_shared_phy = true,
> -};
> -
> static const struct of_device_id meson_pcie_of_match[] = {
> {
> .compatible = "amlogic,axg-pcie",
> - .data = &meson_pcie_axg_param,
> },
> {
> .compatible = "amlogic,g12a-pcie",
> - .data = &meson_pcie_g12a_param,
> },
> {},
> };
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
next prev parent reply other threads:[~2020-01-24 8:27 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-23 23:29 [PATCH v6 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 1/7] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2020-01-24 8:27 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 2/7] dt-bindings: Add AXG shared MIPI/PCIE analog " Remi Pommarel
2020-01-24 8:28 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 3/7] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
2020-01-24 8:30 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 4/7] arm64: dts: meson-axg: Add PCIE PHY nodes Remi Pommarel
2020-01-24 8:34 ` Remi Pommarel
2020-01-23 23:29 ` [PATCH v6 5/7] phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver Remi Pommarel
2020-01-24 8:32 ` Remi Pommarel
2020-03-03 17:19 ` Lorenzo Pieralisi
2020-03-04 9:08 ` Neil Armstrong
2020-03-04 10:44 ` Lorenzo Pieralisi
2020-01-23 23:29 ` [PATCH v6 6/7] phy: amlogic: Add Amlogic AXG PCIE " Remi Pommarel
2020-03-04 10:47 ` Neil Armstrong
2020-03-04 11:01 ` Kishon Vijay Abraham I
2020-03-04 13:08 ` Remi Pommarel
2020-03-05 4:56 ` Kishon Vijay Abraham I
2020-03-05 7:00 ` Neil Armstrong
2020-01-23 23:29 ` [PATCH v6 7/7] PCI: amlogic: Use AXG PCIE Remi Pommarel
2020-01-24 8:35 ` Remi Pommarel [this message]
2020-01-24 8:02 ` [PATCH v6 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Neil Armstrong
2020-01-24 8:37 ` Remi Pommarel
2020-02-24 14:15 ` Lorenzo Pieralisi
2020-02-29 16:07 ` Kevin Hilman
2020-02-29 17:10 ` Remi Pommarel
2020-03-03 15:03 ` Lorenzo Pieralisi
2020-03-04 12:28 ` Lorenzo Pieralisi
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