From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7F6BC3F2CF for ; Fri, 28 Feb 2020 02:18:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0C3B2469F for ; Fri, 28 Feb 2020 02:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730439AbgB1CS5 (ORCPT ); Thu, 27 Feb 2020 21:18:57 -0500 Received: from mga18.intel.com ([134.134.136.126]:64154 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730343AbgB1CS5 (ORCPT ); Thu, 27 Feb 2020 21:18:57 -0500 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2020 18:18:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,493,1574150400"; d="scan'208";a="437264890" Received: from otc-nc-03.jf.intel.com (HELO otc-nc-03) ([10.54.39.25]) by fmsmga005.fm.intel.com with ESMTP; 27 Feb 2020 18:18:55 -0800 Date: Thu, 27 Feb 2020 18:18:55 -0800 From: "Raj, Ashok" To: Sinan Kaya Cc: Bjorn Helgaas , "Spassov, Stanislav" , "corbet@lwn.net" , "alex.williamson@redhat.com" , "tglx@linutronix.de" , "Wang, Wei" , "akpm@linux-foundation.org" , "Schoenherr, Jan H." , "rajatja@google.com" , "linux-pci@vger.kernel.org" , "linux-doc@vger.kernel.org" , Ashok Raj Subject: Re: [PATCH 1/3] PCI: Make PCIE_RESET_READY_POLL_MS configurable Message-ID: <20200228021855.GA57330@otc-nc-03> References: <20200227214534.GA143139@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Feb 27, 2020 at 06:44:56PM -0500, Sinan Kaya wrote: > On 2/27/2020 4:45 PM, Bjorn Helgaas wrote: > > The 60 second timeout came from 821cdad5c46c ("PCI: Wait up to 60 > > seconds for device to become ready after FLR") and is probably too > > long. We probably should pick a smaller value based on numbers from > > the spec and make quirks for devices that needed more time. > > If I remember right, there was no time mention about how long to > wait. Spec says device should send CRS as long as it is not ready. Not exactly.. there are some requirements to follow for rules after a conventional reset. Look for "The second set of rules addresses requirements placed on the system" i'm looking a the 5.0 spec (around page 553) :-). In general 1s seems good enough for most cases. For ports that support > 5gt/s transfer speed, it says 100ms after link training completes. I'm not sure if this means 100ms after getting a DLLSC event?