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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	Ravikiran Gummaluri <rgummal@xilinx.com>,
	maz@kernel.org
Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Date: Fri, 28 Feb 2020 10:44:42 +0000	[thread overview]
Message-ID: <20200228104442.GA2874@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <MN2PR02MB63365B50058B35AA37341BC9A5ED0@MN2PR02MB6336.namprd02.prod.outlook.com>

[+MarcZ, FHI]

On Tue, Feb 25, 2020 at 02:39:56PM +0000, Bharat Kumar Gogada wrote:

[...]

> > > +/* ECAM definitions */
> > > +#define ECAM_BUS_NUM_SHIFT		20
> > > +#define ECAM_DEV_NUM_SHIFT		12
> > 
> > You don't need these ECAM_* defines, you can use pci_generic_ecam_ops.
> Does this need separate ranges region for ECAM space ? 
> We have ECAM and controller space in same region.

You can create an ECAM window with pci_ecam_create where *cfgres
represent the ECAM area, I don't get what you mean by "same region".

Do you mean "contiguous" ? Or something else ?

> > > +
> > > +/**
> > > + * struct xilinx_cpm_pcie_port - PCIe port information
> > > + * @reg_base: Bridge Register Base
> > > + * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
> > > + * @irq: Interrupt number
> > > + * @root_busno: Root Bus number
> > > + * @dev: Device pointer
> > > + * @leg_domain: Legacy IRQ domain pointer
> > > + * @irq_misc: Legacy and error interrupt number  */ struct
> > > +xilinx_cpm_pcie_port {
> > > +	void __iomem *reg_base;
> > > +	void __iomem *cpm_base;
> > > +	u32 irq;
> > > +	u8 root_busno;
> > > +	struct device *dev;
> > > +	struct irq_domain *leg_domain;
> > > +	int irq_misc;
> > > +};
> > > +
> > > +static inline u32 pcie_read(struct xilinx_cpm_pcie_port *port, u32
> > > +reg) {
> > > +	return readl(port->reg_base + reg);
> > > +}
> > > +
> > > +static inline void pcie_write(struct xilinx_cpm_pcie_port *port,
> > > +			      u32 val, u32 reg)
> > > +{
> > > +	writel(val, port->reg_base + reg);
> > > +}
> > > +
> > > +static inline bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port
> > > +*port) {
> > > +	return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) &
> > > +		XILINX_CPM_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
> > 
> > 	u32 val = pcie_read(port, XILINX_CPM_PCIE_REG_PSCR);
> > 
> > 	return val & XILINX_CPM_PCIE_REG_PSCR_LNKUP;
> > 
> > And this function call is not that informative anyway - it is used just to print a log
> > whose usefulness is questionable.
> We need this logging information customers are using this info in case
> of link down failure.

Out of curiosity, to do what ?

[...]

> > > +/**
> > > + * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark
> > > +IRQ as valid
> > > + * @domain: IRQ domain
> > > + * @irq: Virtual IRQ number
> > > + * @hwirq: HW interrupt number
> > > + *
> > > + * Return: Always returns 0.
> > > + */
> > > +static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain,
> > > +				    unsigned int irq, irq_hw_number_t hwirq) {
> > > +	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
> > 
> > INTX are level IRQs, the flow handler must be handle_level_irq.
> Accepted will change.
> > 
> > > +	irq_set_chip_data(irq, domain->host_data);
> > > +	irq_set_status_flags(irq, IRQ_LEVEL);
> > 
> > The way INTX are handled in this patch is wrong. You must set-up a chained IRQ
> > with the appropriate flow handler, current code uses an IRQ action and that's an
> > IRQ layer violation and it goes without saying that it is almost certainly broken.
> In our controller we use same irq line for controller errors and
> legacy errors.  we have two cases here where error interrupts are
> self-consumed by controller, and legacy interrupts are flow handled.
> Its not INTX handling alone for this IRQ line .  So chained IRQ can be
> used for self consumed interrupts too ?

No. In this specific case both solutions are not satisfying, we need to
give it some thought, I will talk to Marc (CC'ed) to find the best
option here going forward.

Thanks,
Lorenzo

  reply	other threads:[~2020-02-28 10:44 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-30 16:12 [PATCH v5 0/2] Adding support for Versal CPM as Root Port driver Bharat Kumar Gogada
2020-01-30 16:12 ` [PATCH v5 1/2] PCI: xilinx-cpm: Add device tree binding for Versal CPM host bridge Bharat Kumar Gogada
2020-01-30 16:12 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Bharat Kumar Gogada
2020-02-17  4:54   ` Bharat Kumar Gogada
2020-02-17 23:55   ` Bjorn Helgaas
2020-02-24  9:14     ` Bharat Kumar Gogada
2020-02-25 11:30   ` Lorenzo Pieralisi
2020-02-25 11:40   ` Lorenzo Pieralisi
2020-02-25 14:39     ` Bharat Kumar Gogada
2020-02-28 10:44       ` Lorenzo Pieralisi [this message]
2020-02-28 12:48         ` Bharat Kumar Gogada
2020-03-06 11:16           ` Lorenzo Pieralisi
2020-03-06 11:45             ` Bharat Kumar Gogada
2020-03-06 15:12               ` Lorenzo Pieralisi
2020-03-09 11:27                 ` Bharat Kumar Gogada
2020-03-16  5:24         ` Bharat Kumar Gogada
2020-03-30  9:37           ` Bharat Kumar Gogada
2020-04-16  7:07             ` Bharat Kumar Gogada
2020-04-20  8:52               ` Lorenzo Pieralisi

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