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* [PATCH v2 00/17] Improve PCI device post-reset readiness polling
@ 2020-03-02 18:44 Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 01/17] PCI: Fall back to slot/bus reset if softer methods timeout Stanislav Spassov
                   ` (16 more replies)
  0 siblings, 17 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

The first version of this patch series can be found here:
https://lore.kernel.org/linux-pci/20200223122057.6504-1-stanspas@amazon.com

Originally, this patch series aimed to only solve an issue where
pci_dev_wait can cause system crashes. After a reset, a hung device may
keep responding with CRS completions indefinitely. If CRS Software
Visibility is enabled on the Root Port, attempting to read any register
other than PCI_VENDOR_ID will cause the Root Port to autonomously retry
the request without reporting back to the CPU core. Unless the number of
retries or the amount of time spent retrying is limited by
platform-specific means, this scenario leads to low-level platform
timeouts (such as a TOR Timeout), which easily escalate to a crash.

The feedback on the first version of this patch series inspired a
deeper dive into the PCI Firmware Spec (_DSM functions 8 and 9),
which revealed several different types of delays that can be overriden
on a per-device basis to avoid waiting for too long on device that are
known to come back quickly after reset. The kernel already stores such
overrides for some, but not all of the delays.

While adding the infrastructure to allow overriding delays, I discovered
and addressed several inconsistencies between what the PCIE
Base Specification says and what the code does, and came up with more
improvements all around device resets and readiness polling.

This patch series now paves the way for Readiness Time Reporting capability
support, and touches upon (in comments) some changes that would be
required for supporting Readiness Notifications.

Stanislav Spassov (17):
  PCI: Fall back to slot/bus reset if softer methods timeout
  PCI: Remove unused PCI_PM_BUS_WAIT
  PCI: Use pci_bridge_wait_for_secondary_bus after SBR
  PCI: Do not override delay for D0->D3hot transition
  PCI: Fix handling of _DSM 8 (avoiding reset delays)
  PCI: Fix us->ms conversion in pci_acpi_optimize_delay
  PCI: Clean up and document PM/reset delays
  PCI: Add more delay overrides to struct pci_dev
  PCI: Generalize pci_bus_max_d3cold_delay to pci_bus_max_delay
  PCI: Use correct delay in pci_bridge_wait_for_secondary_bus
  PCI: Refactor pci_dev_wait to remove timeout parameter
  PCI: Refactor pci_dev_wait to take pci_init_event
  PCI: Cache CRS Software Visibiliy in struct pci_dev
  PCI: Introduce per-device reset_ready_poll override
  PCI: Refactor polling loop out of pci_dev_wait
  PCI: Add CRS handling to pci_dev_wait()
  PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s

 Documentation/power/pci.rst         |   4 +-
 arch/x86/pci/intel_mid_pci.c        |   2 +-
 drivers/hid/intel-ish-hid/ipc/ipc.c |   2 +-
 drivers/mfd/intel-lpss-pci.c        |   2 +-
 drivers/net/ethernet/marvell/sky2.c |   2 +-
 drivers/pci/iov.c                   |   4 +-
 drivers/pci/pci-acpi.c              | 106 +++++++++----
 drivers/pci/pci-driver.c            |   4 +-
 drivers/pci/pci.c                   | 233 +++++++++++++++++++---------
 drivers/pci/pci.h                   |  81 +++++++++-
 drivers/pci/probe.c                 |  10 +-
 drivers/pci/quirks.c                |   9 +-
 include/linux/pci-acpi.h            |   8 +-
 include/linux/pci.h                 |  45 +++++-
 14 files changed, 388 insertions(+), 124 deletions(-)


base-commit: bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH v2 01/17] PCI: Fall back to slot/bus reset if softer methods timeout
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 02/17] PCI: Remove unused PCI_PM_BUS_WAIT Stanislav Spassov
                   ` (15 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Previously, if a device never came back (i.e., never started returning
Successful Completions for Configuration Requests) after a reset, they
would return -ENOTTY, causing __pci_reset_function_locked to move on
to the next reset method.

However, up until slot/bus reset, all of them rely on the device being
responsive and are therefore not safe to attempt in this situation.

This patch introduces ETIMEDOUT as a new, specially handled return value
for the reset methods (which all end in "return pci_dev_wait"), to allow
skipping to slot/bus reset where appropriate.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d828ca835a98..ac8504d75c32 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1043,7 +1043,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
 		if (delay > timeout) {
 			pci_warn(dev, "not ready %dms after %s; giving up\n",
 				 delay - 1, reset_type);
-			return -ENOTTY;
+			return -ETIMEDOUT;
 		}
 
 		if (delay > 1000)
@@ -4845,6 +4845,7 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
 	if (probe)
 		return 0;
 
+	/* XXX: Shouldn't this lock the bus? */
 	return pci_bridge_secondary_bus_reset(dev->bus->self);
 }
 
@@ -4979,25 +4980,37 @@ int __pci_reset_function_locked(struct pci_dev *dev)
 	/*
 	 * A reset method returns -ENOTTY if it doesn't support this device
 	 * and we should try the next method.
+	 * It returns -ETIMEDOUT if the device never became responsive after
+	 * the reset: we jump to the reset types that do not rely on config
+	 * space access (if any are left).
 	 *
-	 * If it returns 0 (success), we're finished.  If it returns any
-	 * other error, we're also finished: this indicates that further
-	 * reset mechanisms might be broken on the device.
+	 * If it returns 0 (success), we are finished.
+	 * If it returns any other error, we are finished (something must have
+	 * went terribly wrong and it is not safe to continue reset attempts).
 	 */
 	rc = pci_dev_specific_reset(dev, 0);
+	if (rc == -ETIMEDOUT)
+		goto unresponsive;
 	if (rc != -ENOTTY)
 		return rc;
 	if (pcie_has_flr(dev)) {
 		rc = pcie_flr(dev);
+		if (rc == -ETIMEDOUT)
+			goto unresponsive;
 		if (rc != -ENOTTY)
 			return rc;
 	}
 	rc = pci_af_flr(dev, 0);
+	if (rc == -ETIMEDOUT)
+		goto unresponsive;
 	if (rc != -ENOTTY)
 		return rc;
 	rc = pci_pm_reset(dev, 0);
+	if (rc == -ETIMEDOUT)
+		goto unresponsive;
 	if (rc != -ENOTTY)
 		return rc;
+unresponsive:
 	rc = pci_dev_reset_slot_function(dev, 0);
 	if (rc != -ENOTTY)
 		return rc;
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 02/17] PCI: Remove unused PCI_PM_BUS_WAIT
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 01/17] PCI: Fall back to slot/bus reset if softer methods timeout Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 03/17] PCI: Use pci_bridge_wait_for_secondary_bus after SBR Stanislav Spassov
                   ` (14 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

The last usage of this constant was removed by:
commit 476e7faefc43 ("PCI PM: Do not wait for buses in B2 or B3 during resume")

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 6394e7746fb5..659ab3f9042a 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -46,7 +46,6 @@ int pci_bus_error_reset(struct pci_dev *dev);
 #define PCI_PM_D2_DELAY         200
 #define PCI_PM_D3_WAIT          10
 #define PCI_PM_D3COLD_WAIT      100
-#define PCI_PM_BUS_WAIT         50
 
 /**
  * struct pci_platform_pm_ops - Firmware PM callbacks
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 03/17] PCI: Use pci_bridge_wait_for_secondary_bus after SBR
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 01/17] PCI: Fall back to slot/bus reset if softer methods timeout Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 02/17] PCI: Remove unused PCI_PM_BUS_WAIT Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 04/17] PCI: Do not override delay for D0->D3hot transition Stanislav Spassov
                   ` (13 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

So far, pci_bridge_wait_for_secondary_bus() was only invoked by PM code
after (runtime) resume of devices, but it naturally makes sense for
handling post-SBR waiting as well.

It uses the PCI_PM_D3COLD_WAIT value (100ms), potentially overridden on
a per-device basis to a lower-value, as the basis for determining
how long to wait, and handles special cases such as legacy PCI devices
(requiring Trhfa), and the different starting points for the waiting
time depending on PCIe port speed.

On PCI Express, there will be cases where the new code sleeps far less
than the 1s being replaced by this patch. This should be okay, because
PCI Express Base Specification Revision 5.0 Version 1.0 (May 22, 2019)
in Section 6.6.1 "Conventional Reset" only notes 100ms as the minimum
waiting time. After this time, the OS is permitted to issue
Configuration Requests, but it is possible that the device responds
with Configuration Request Retry Status (CRS) Completions, rather than
Successful Completion. Returning CRS can go on for up to 1 second after
a Conventional Reset (such as SBR) before the OS can consider the device
broken. This additional wait is handled by pci_dev_wait.

Currently, the only callchain that lands in the function modified by
this patch starts at pci_bridge_secondary_bus_reset which invokes
one out of two versions of pcibios_reset_secondary_bus that both end
with a call to pci_reset_secondary_bus.
Afterwards, pci_bridge_secondary_bus_reset always invokes pci_dev_wait.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ac8504d75c32..c1a866f733e9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4800,14 +4800,7 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 
-	/*
-	 * Trhfa for conventional PCI is 2^25 clock cycles.
-	 * Assuming a minimum 33MHz clock this results in a 1s
-	 * delay before we can consider subordinate devices to
-	 * be re-initialized.  PCIe has some ways to shorten this,
-	 * but we don't make use of them yet.
-	 */
-	ssleep(1);
+	pci_bridge_wait_for_secondary_bus(dev);
 }
 
 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 04/17] PCI: Do not override delay for D0->D3hot transition
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (2 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 03/17] PCI: Use pci_bridge_wait_for_secondary_bus after SBR Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 05/17] PCI: Fix handling of _DSM 8 (avoiding reset delays) Stanislav Spassov
                   ` (12 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Both specifications that document mechanisms for overriding the
D3hot->D0 waiting time only speak of this specific direction.
Nothing is mentioned about the opposite (D*->D3hot) except for
the default value of 10ms in PCI Express Base Specification
r5.0 (May 22, 2019), Section 5.9 "State Transition Recovery Time
Requirements".

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index c1a866f733e9..03103bb15b42 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4589,7 +4589,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
 	csr &= ~PCI_PM_CTRL_STATE_MASK;
 	csr |= PCI_D3hot;
 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-	pci_dev_d3_sleep(dev);
+	msleep(PCI_PM_D3_WAIT);
 
 	csr &= ~PCI_PM_CTRL_STATE_MASK;
 	csr |= PCI_D0;
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 05/17] PCI: Fix handling of _DSM 8 (avoiding reset delays)
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (3 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 04/17] PCI: Do not override delay for D0->D3hot transition Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay Stanislav Spassov
                   ` (11 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

On Sx Resume (boot from ACPI S5, resume from ACPI S4 or S3), platform
firmware may enforce that sufficient time has passed to cover the
mandatory (per PCI Express Specification) power-on reset delays of
all PCI devices before control is handed over to the operating system.
To avoid duplicated waiting by the OS, the firmware uses _DSM 8 in the
ACPI scope of a PCI host bus to inform the OS that for the whole PCI
subsystem underneath that host bridge, power-on reset delays are being
covered by firmware.

Previously, the kernel used _DSM 8 to override the d3cold_delay value
stored in struct pci_dev to 0. However, the assumption that the delay
is covered by firmware when _DSM 8 returns 1 only holds for the
firmware-initiated resets as part of Sx Resume flows. If an OS has the
ability to apply Conventional Reset to devices without system firmware
involvement, then it still needs to adhere to the usual reset delays.

Runtime Device Power Management triggering a D3cold->D0 transition
is an existing example of the kernel not involving system firmware.
Another example is the OS triggering Secondary Bus Reset by setting
the SBR bit in the Bridge Control register of any Port device.

In preparation for future work to improve post-reset delays, this patch
preserves the value of d3cold_delay even when _DSM 8 returns 1.
The decision not to wait after resume is instead taken at a higher level
in pci_bridge_wait_for_secondary_bus based on a new parameter that
indicates whether the waiting is due to an Sx Resume event.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci-acpi.c   | 65 ++++++++++++++++++++++++++++++----------
 drivers/pci/pci-driver.c |  4 +--
 drivers/pci/pci.c        | 11 +++++--
 drivers/pci/pci.h        |  2 +-
 include/linux/pci-acpi.h |  8 ++---
 include/linux/pci.h      |  4 ++-
 6 files changed, 67 insertions(+), 27 deletions(-)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 0c02d500158f..a8fa13d6089d 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1120,21 +1120,35 @@ void acpi_pci_add_bus(struct pci_bus *bus)
 	acpi_pci_slot_enumerate(bus);
 	acpiphp_enumerate_slots(bus);
 
-	/*
-	 * For a host bridge, check its _DSM for function 8 and if
-	 * that is available, mark it in pci_host_bridge.
+	/* For a host bridge, check _DSM function 8 and if that returns 1,
+	 * mark it in the pci_host_bridge.
+	 *
+	 * Function 8, "Avoid Power-On Reset Delay Duplication on Sx Resume"
+	 * applies to the entire hierarchy below a PCI host bridge.
+	 * If it returns one, the OS may assume that all devices in the
+	 * hierarchy have already completed power-on reset delays
+	 * before FW handed over control to the OS on Sx Resume (such as boot
+	 * from ACPI S5, or resume from ACPI S4 or S3 states).
+	 * This _DSM is applicable whether reductions in device readiness
+	 * timing, via Readiness Notification or _DSM function 9, are available
+	 * or not.
+	 *
+	 * This _DSM function is defined by the PCI Firmware Specification
+	 * Revision 3.2 (January 26, 2015), after originally introduced by a
+	 * draft ECN of January 28, 2014, titled "ACPI additions for FW latency
+	 * optimizations."
 	 */
 	if (!pci_is_root_bus(bus))
 		return;
 
 	obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3,
-				RESET_DELAY_DSM, NULL);
+				IGNORE_RESET_DELAY_ON_SX_RESUME_DSM, NULL);
 	if (!obj)
 		return;
 
 	if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
 		bridge = pci_find_host_bridge(bus);
-		bridge->ignore_reset_delay = 1;
+		bridge->ignore_reset_delay_on_sx_resume = 1;
 	}
 	ACPI_FREE(obj);
 }
@@ -1168,19 +1182,38 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
  * @handle: ACPI handle of this device
  *
  * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
- * control method of either the device itself or the PCI host bridge.
- *
- * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
- * host bridge.  If it returns one, the OS may assume that all devices in
- * the hierarchy have already completed power-on reset delays.
+ * Function 9 of the device, and cache the parent host bridge's flag for
+ * ignoring reset delay upon Sx Resume (the flag is originally set in
+ * acpi_pci_add_bus through _DSM Function 8).
  *
  * Function 9, "Device Readiness Durations," applies only to the object
  * where it is located.  It returns delay durations required after various
- * events if the device requires less time than the spec requires.  Delays
- * from this function take precedence over the Reset Delay function.
+ * events if the device requires less time than the spec requires.
+ * Values provided by this function can only be used to lower (reduce) the
+ * latency required by specification or values discovered from device.
+ *
+ * This _DSM function is defined by the PCI Firmware Specification Rev 3.2
+ * (January 26, 2015), after originally introduced by a draft ECN of
+ * January 28, 2014, titled "ACPI additions for FW latency optimizations."
  *
- * These _DSM functions are defined by the draft ECN of January 28, 2014,
- * titled "ACPI additions for FW latency optimizations."
+ * XXX The PCI Firmware Specification contradicts itself by stating, in addition
+ * to the above "can only be used to lower (reduce)", that also:
+ * Values must be interpreted as overriding any Configuration Ready indicator
+ * from hardware, whether increasing or decreasing required delays. This
+ * includes ignoring FRS and DRS notifications where overridden by this
+ * _DSM function, as well as ignoring values specified in the Readiness Time
+ * Reporting Extended Capability, if present.
+ * Meanwhile, the PCI Express Base Specification Revision 5.0 Version 1.0
+ * (22 May 2019) states in section 7.9.17 Readiness Time Reporting Extended
+ * Capability:
+ * Software is permitted to issue requests upon the earliest of:
+ * - Receiving a Readiness Notification messages
+ * - Waiting the appropriate time as per relevant specifications
+ * - Waiting the time indicated in the associated field of this capability
+ * - Waiting the time defined by system software or firmware
+ * The kernel does not yet support Readiness Notifications, and does not yet
+ * use a Readiness Time Reporting capability if present, so we do not need to
+ * worry about the prioritization for now.
  */
 static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 				    acpi_handle handle)
@@ -1189,8 +1222,8 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 	int value;
 	union acpi_object *obj, *elements;
 
-	if (bridge->ignore_reset_delay)
-		pdev->d3cold_delay = 0;
+	pdev->ignore_reset_delay_on_sx_resume =
+		bridge->ignore_reset_delay_on_sx_resume;
 
 	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 3,
 				FUNCTION_DELAY_DSM, NULL);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 0454ca0e4e3f..7e8ca8115c4f 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -917,7 +917,7 @@ static int pci_pm_resume_noirq(struct device *dev)
 	pcie_pme_root_status_cleanup(pci_dev);
 
 	if (!skip_bus_pm && prev_state == PCI_D3cold)
-		pci_bridge_wait_for_secondary_bus(pci_dev);
+		pci_bridge_wait_for_secondary_bus(pci_dev, true);
 
 	if (pci_has_legacy_pm_support(pci_dev))
 		return 0;
@@ -1321,7 +1321,7 @@ static int pci_pm_runtime_resume(struct device *dev)
 	pci_pm_default_resume(pci_dev);
 
 	if (prev_state == PCI_D3cold)
-		pci_bridge_wait_for_secondary_bus(pci_dev);
+		pci_bridge_wait_for_secondary_bus(pci_dev, false);
 
 	if (pm && pm->runtime_resume)
 		error = pm->runtime_resume(dev);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 03103bb15b42..4899b12b5a38 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2843,6 +2843,7 @@ void pci_pm_init(struct pci_dev *dev)
 	}
 
 	dev->pm_cap = pm;
+	dev->ignore_reset_delay_on_sx_resume = 0;
 	dev->d3_delay = PCI_PM_D3_WAIT;
 	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
 	dev->bridge_d3 = pci_bridge_d3_possible(dev);
@@ -4698,7 +4699,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
  * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
  * 4.3.2.
  */
-void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
+void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, bool sx_resume)
 {
 	struct pci_dev *child;
 	int delay;
@@ -4723,7 +4724,11 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
 	}
 
 	/* Take d3cold_delay requirements into account */
-	delay = pci_bus_max_d3cold_delay(dev->subordinate);
+	if (sx_resume && dev->ignore_reset_delay_on_sx_resume)
+		delay = 0;
+	else
+		delay = pci_bus_max_d3cold_delay(dev->subordinate);
+
 	if (!delay) {
 		up_read(&pci_bus_sem);
 		return;
@@ -4800,7 +4805,7 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 
-	pci_bridge_wait_for_secondary_bus(dev);
+	pci_bridge_wait_for_secondary_bus(dev, false);
 }
 
 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 659ab3f9042a..c4c3ba926f45 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -107,7 +107,7 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev);
 void pci_free_cap_save_buffers(struct pci_dev *dev);
 bool pci_bridge_d3_possible(struct pci_dev *dev);
 void pci_bridge_d3_update(struct pci_dev *dev);
-void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
+void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, bool sx_resume);
 
 static inline void pci_wakeup_event(struct pci_dev *dev)
 {
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 62b7fdcc661c..99865773d65e 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -107,10 +107,10 @@ static inline void acpiphp_check_host_bridge(struct acpi_device *adev) { }
 #endif
 
 extern const guid_t pci_acpi_dsm_guid;
-#define IGNORE_PCI_BOOT_CONFIG_DSM	0x05
-#define DEVICE_LABEL_DSM		0x07
-#define RESET_DELAY_DSM			0x08
-#define FUNCTION_DELAY_DSM		0x09
+#define IGNORE_PCI_BOOT_CONFIG_DSM		0x05
+#define DEVICE_LABEL_DSM			0x07
+#define IGNORE_RESET_DELAY_ON_SX_RESUME_DSM	0x08
+#define FUNCTION_DELAY_DSM			0x09
 
 #else	/* CONFIG_ACPI */
 static inline void acpi_pci_add_bus(struct pci_bus *bus) { }
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3840a541a9de..22a5b7164c32 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -354,6 +354,8 @@ struct pci_dev {
 						      user sysfs */
 	unsigned int	clear_retrain_link:1;	/* Need to clear Retrain Link
 						   bit manually */
+	unsigned int    ignore_reset_delay_on_sx_resume:1; /* Cached value from
+							      pci_host_bridge */
 	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
 	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
 
@@ -503,7 +505,7 @@ struct pci_host_bridge {
 	void (*release_fn)(struct pci_host_bridge *);
 	void		*release_data;
 	struct msi_controller *msi;
-	unsigned int	ignore_reset_delay:1;	/* For entire hierarchy */
+	unsigned int	ignore_reset_delay_on_sx_resume:1;	/* For entire hierarchy */
 	unsigned int	no_ext_tags:1;		/* No Extended Tags */
 	unsigned int	native_aer:1;		/* OS may use PCIe AER */
 	unsigned int	native_pcie_hotplug:1;	/* OS may use PCIe hotplug */
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (4 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 05/17] PCI: Fix handling of _DSM 8 (avoiding reset delays) Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-03  4:19   ` kbuild test robot
  2020-03-03  5:54   ` kbuild test robot
  2020-03-02 18:44 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays Stanislav Spassov
                   ` (10 subsequent siblings)
  16 siblings, 2 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

_DSM Function 9 returns device readiness durations in microseconds.

Without this fix, integer truncation could cause msleep()-ing for up to
999us less than actually requested by the firmware.

Specifically, if the firmware specifies a 500us delay, msleep(0) would
be invoked by the users of the delay values optimized here.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci-acpi.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index a8fa13d6089d..508924377bff 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1219,6 +1219,11 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 				    acpi_handle handle)
 {
 	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
+	/*
+	 * _DSM 9 provides values in microseconds, but the kernel uses msleep()
+	 * when waiting, so the code below rounds up when setting value in ms
+	 */
+	u64 value_us;
 	int value;
 	union acpi_object *obj, *elements;
 
@@ -1233,12 +1238,18 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
 		elements = obj->package.elements;
 		if (elements[0].type == ACPI_TYPE_INTEGER) {
-			value = (int)elements[0].integer.value / 1000;
+			value_us = elements[0].integer.value;
+			value = (int)(value_us / 1000);
+			if (value_us % 1000 > 0)
+				value++;
 			if (value < PCI_PM_D3COLD_WAIT)
 				pdev->d3cold_delay = value;
 		}
 		if (elements[3].type == ACPI_TYPE_INTEGER) {
-			value = (int)elements[3].integer.value / 1000;
+			value_us = elements[3].integer.value;
+			value = (int)(value_us / 1000);
+			if (value_us % 1000 > 0)
+				value++;
 			if (value < PCI_PM_D3_WAIT)
 				pdev->d3_delay = value;
 		}
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 07/17] PCI: Clean up and document PM/reset delays
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (5 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-03  1:51   ` kbuild test robot
  2020-03-03  2:54   ` kbuild test robot
  2020-03-02 18:44 ` [PATCH v2 08/17] PCI: Add more delay overrides to struct pci_dev Stanislav Spassov
                   ` (9 subsequent siblings)
  16 siblings, 2 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

...and replace several "magic numbers" scattered throughout the code.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/iov.c      |  4 +--
 drivers/pci/pci-acpi.c |  4 +--
 drivers/pci/pci.c      | 21 +++---------
 drivers/pci/pci.h      | 72 ++++++++++++++++++++++++++++++++++++++++--
 4 files changed, 78 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 4d1f392b05f9..d4e4a0c0a97f 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -524,7 +524,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
 	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
 	pci_cfg_access_lock(dev);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
-	msleep(100);
+	msleep(PCI_VF_ENABLE_DELAY);
 	pci_cfg_access_unlock(dev);
 
 	rc = sriov_add_vfs(dev, initial);
@@ -735,7 +735,7 @@ static void sriov_restore_state(struct pci_dev *dev)
 	pci_iov_set_numvfs(dev, iov->num_VFs);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
 	if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
-		msleep(100);
+		msleep(PCI_VF_ENABLE_DELAY);
 }
 
 /**
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 508924377bff..66e8f8199ce0 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1242,7 +1242,7 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 			value = (int)(value_us / 1000);
 			if (value_us % 1000 > 0)
 				value++;
-			if (value < PCI_PM_D3COLD_WAIT)
+			if (value < PCI_RESET_DELAY)
 				pdev->d3cold_delay = value;
 		}
 		if (elements[3].type == ACPI_TYPE_INTEGER) {
@@ -1250,7 +1250,7 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 			value = (int)(value_us / 1000);
 			if (value_us % 1000 > 0)
 				value++;
-			if (value < PCI_PM_D3_WAIT)
+			if (value < PCI_PM_D3HOT_DELAY)
 				pdev->d3_delay = value;
 		}
 	}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4899b12b5a38..aaef00578487 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2844,8 +2844,8 @@ void pci_pm_init(struct pci_dev *dev)
 
 	dev->pm_cap = pm;
 	dev->ignore_reset_delay_on_sx_resume = 0;
-	dev->d3_delay = PCI_PM_D3_WAIT;
-	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
+	dev->d3_delay = PCI_PM_D3HOT_DELAY;
+	dev->d3cold_delay = PCI_RESET_DELAY;
 	dev->bridge_d3 = pci_bridge_d3_possible(dev);
 	dev->d3cold_allowed = true;
 
@@ -4500,12 +4500,7 @@ int pcie_flr(struct pci_dev *dev)
 	if (dev->imm_ready)
 		return 0;
 
-	/*
-	 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
-	 * 100ms, but may silently discard requests while the FLR is in
-	 * progress.  Wait 100ms before trying to access the device.
-	 */
-	msleep(100);
+	msleep(PCI_FLR_DELAY);
 
 	return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
 }
@@ -4544,13 +4539,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
 	if (dev->imm_ready)
 		return 0;
 
-	/*
-	 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
-	 * updated 27 July 2006; a device must complete an FLR within
-	 * 100ms, but may silently discard requests while the FLR is in
-	 * progress.  Wait 100ms before trying to access the device.
-	 */
-	msleep(100);
+	msleep(PCI_FLR_DELAY);
 
 	return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
 }
@@ -4590,7 +4579,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
 	csr &= ~PCI_PM_CTRL_STATE_MASK;
 	csr |= PCI_D3hot;
 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
-	msleep(PCI_PM_D3_WAIT);
+	msleep(PCI_PM_D3HOT_DELAY);
 
 	csr &= ~PCI_PM_CTRL_STATE_MASK;
 	csr |= PCI_D0;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index c4c3ba926f45..9b5dd6ea2f52 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -43,9 +43,75 @@ int pci_probe_reset_function(struct pci_dev *dev);
 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
 int pci_bus_error_reset(struct pci_dev *dev);
 
-#define PCI_PM_D2_DELAY         200
-#define PCI_PM_D3_WAIT          10
-#define PCI_PM_D3COLD_WAIT      100
+/*
+ * These constants represent the minimum amounts of time mandated by the
+ * PCI Express Base specification that software needs to wait after
+ * various PCI device events involving (re-)initialization. Only after
+ * the appropriate delay has elapsed, is software permitted to issue
+ * Configuration Requests targeting the affected device.
+ *
+ * Relevant sections in PCI Express Base Specification r5.0 (May 22, 2019):
+ * - 6.6.1 "Conventional Reset" for PCI_RESET_DELAY and PCI_DL_UP_DELAY
+ * - 6.6.2 "Function Level Reset" for PCI_FLR_DELAY
+ * - 5.9 "State Transition Recovery Time Requirements" for PCI_PM_D3HOT_DELAY
+ *        and PCI_PM_D2_DELAY
+ * - 9.3.3.3.1 "VF Enable" for PCI_VF_ENABLE_DELAY
+ *
+ * There are mechanisms to reduce some of the delay values for specific devices:
+ * - a device may expose the Readiness Time Reporting Extended Capability from:
+ *   PCI Express Base Specification r4.0 (September 27, 2017), sec 7.9.17
+ *   (This is currently not supported by the kernel.)
+ * - system firmware may provide overrides using an ACPI _DSM Function 9:
+ *   PCI Firmware Specification r3.2 (January 26, 2015), sec 4.6.9
+ *   (see pci_acpi_optimize_delay)
+ *
+ * Unless overridden by _DSM Function 9, other mechanisms may be used to reduce
+ * or completely avoid some of the delays:
+ * - Readiness Notifications (DRS and FRS)
+ * - the Immediate Readiness bit of the Status Register in the PCI header
+ * - the Immediate_Readiness_on_Return_to_D0 in the Power Management
+ *   Capabilities Register in the PCI Power Management Capability
+ * (None of these are currently supported by the kernel.)
+ *
+ * Note: While devices are required to be responsive to Configuration
+ * Requests after these delays, they may not respond with Successful
+ * Completion status until they complete potentially lengthy internal
+ * initialization sequences. Instead, devices respond with Configuration
+ * Request Retry Status (CRS) Completions. Therefore, additional waiting
+ * is necessary as handled by pci_dev_wait().
+ */
+/*
+ * Conventional (non-FLR) reset delay, including D3cold->D0 transitions,
+ * Secondary Bus Reset, and any platform-specific means of triggering
+ * a Conventional Reset.
+ *
+ * According to PCI Firmware spec r3.2, sec 4.6.9, for devices beneath
+ * downstream ports supporting the Data Link Layer Active Reporting
+ * capability, this delay should not be used (see PCI_DL_UP_DELAY).
+ */
+#define PCI_RESET_DELAY		100
+/*
+ * Post-DL_Up (Data Link Layer Active) delay applicable for devices immediately
+ * under a Downstream Port that is capable of reporting Data Link Layer Ready.
+ * Not to be confused with how much time it takes for the link itself to become
+ * active (see pcie_wait_for_link_delay).
+ */
+#define PCI_DL_UP_DELAY		100
+/*
+ * Post-FLR delay
+ * Also applies to legacy devices supporting AF_FLR per Advanced Capabilities
+ * for Conventional PCI ECN, 13 April 2006, updated 27 July 2006)
+ */
+#define PCI_FLR_DELAY		100
+/*
+ * D0/D1/D2->D3hot and D3hot->D0 delay
+ * The specifications do *not* mention overridability of the ->D3hot direction
+ */
+#define PCI_PM_D3HOT_DELAY	10
+/* Post-VF_Enable delay */
+#define PCI_VF_ENABLE_DELAY	100
+/* D0/D1->D2 and D2->D0 delay */
+#define PCI_PM_D2_DELAY		200
 
 /**
  * struct pci_platform_pm_ops - Firmware PM callbacks
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 08/17] PCI: Add more delay overrides to struct pci_dev
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (6 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 09/17] PCI: Generalize pci_bus_max_d3cold_delay to pci_bus_max_delay Stanislav Spassov
                   ` (8 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Almost all of the PCI_*_DELAY constants declared in drivers/pci/pci.h
can be overridden on a per-device basis, as explained in the constants'
comments. To allow storing per-device values, this patch introduces
a type to describe the various "initialization events":
    enum pci_init_event
and an array in struct pci_dev, with an override for each event.

This array is initially populated with the PCI_*_DELAY constants,
but can be later overridden by pci_acpi_optimize_delay. Quirks and
drivers may also end up tweaking the values.

The new array replaces two previous members: d3_delay and d3cold_delay
Direct mentions of PCI_*_DELAY are replaced with the per-device
override where applicable.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 Documentation/power/pci.rst         |  4 ++-
 arch/x86/pci/intel_mid_pci.c        |  2 +-
 drivers/hid/intel-ish-hid/ipc/ipc.c |  2 +-
 drivers/mfd/intel-lpss-pci.c        |  2 +-
 drivers/net/ethernet/marvell/sky2.c |  2 +-
 drivers/pci/iov.c                   |  4 +--
 drivers/pci/pci-acpi.c              | 42 ++++++++++++++++-------------
 drivers/pci/pci.c                   | 36 ++++++++++++++++++-------
 drivers/pci/quirks.c                |  9 ++++---
 include/linux/pci.h                 | 35 ++++++++++++++++++++++--
 10 files changed, 97 insertions(+), 41 deletions(-)

diff --git a/Documentation/power/pci.rst b/Documentation/power/pci.rst
index 0924d29636ad..8136c8a4b150 100644
--- a/Documentation/power/pci.rst
+++ b/Documentation/power/pci.rst
@@ -320,7 +320,9 @@ that these callbacks operate on::
 	unsigned int	d2_support:1;	/* Low power state D2 is supported */
 	unsigned int	no_d1d2:1;	/* D1 and D2 are forbidden */
 	unsigned int	wakeup_prepared:1;  /* Device prepared for wake up */
-	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
+	unsigned int    delay[PCI_INIT_EVENT_COUNT]; /* minimum waiting time
+							after various events
+							in ms */
 	...
   };
 
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 00c62115f39c..b42b14cd0e00 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -322,7 +322,7 @@ static void pci_d3delay_fixup(struct pci_dev *dev)
 	 */
 	if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
 		return;
-	dev->d3_delay = 0;
+	dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] = 0;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
 
diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c b/drivers/hid/intel-ish-hid/ipc/ipc.c
index 8f8dfdf64833..a209b954fbe8 100644
--- a/drivers/hid/intel-ish-hid/ipc/ipc.c
+++ b/drivers/hid/intel-ish-hid/ipc/ipc.c
@@ -755,7 +755,7 @@ static int _ish_hw_reset(struct ishtp_device *dev)
 	csr |= PCI_D3hot;
 	pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
 
-	mdelay(pdev->d3_delay);
+	mdelay(pdev->delay[PCI_INIT_EVENT_D3HOT_TO_D0]);
 
 	csr &= ~PCI_PM_CTRL_STATE_MASK;
 	csr |= PCI_D0;
diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
index c40a6c7d0cf8..5b9e458d0ab1 100644
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -35,7 +35,7 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev,
 	info->mem = &pdev->resource[0];
 	info->irq = pdev->irq;
 
-	pdev->d3cold_delay = 0;
+	pdev->delay[PCI_INIT_EVENT_RESET] = 0;
 
 	/* Probably it is enough to set this for iDMA capable devices only */
 	pci_set_master(pdev);
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index ebfd0ceac884..f808562e389d 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -5100,7 +5100,7 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	INIT_WORK(&hw->restart_work, sky2_restart);
 
 	pci_set_drvdata(pdev, hw);
-	pdev->d3_delay = 300;
+	pdev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] = 300;
 
 	return 0;
 
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index d4e4a0c0a97f..f71fc28b69e6 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -524,7 +524,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
 	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
 	pci_cfg_access_lock(dev);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
-	msleep(PCI_VF_ENABLE_DELAY);
+	msleep(dev->delay[PCI_INIT_EVENT_VF_ENABLE]);
 	pci_cfg_access_unlock(dev);
 
 	rc = sriov_add_vfs(dev, initial);
@@ -735,7 +735,7 @@ static void sriov_restore_state(struct pci_dev *dev)
 	pci_iov_set_numvfs(dev, iov->num_VFs);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
 	if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
-		msleep(PCI_VF_ENABLE_DELAY);
+		msleep(dev->delay[PCI_INIT_EVENT_VF_ENABLE]);
 }
 
 /**
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 66e8f8199ce0..4b5c29d2a5ab 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -1177,11 +1177,11 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
 }
 
 /**
- * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
- * @pdev: the PCI device whose delay is to be updated
+ * pci_acpi_optimize_delay - optimize PCI readiness delays from ACPI
+ * @pdev: the PCI device whose delays are to be updated
  * @handle: ACPI handle of this device
  *
- * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
+ * Update the readiness delays of a PCI device from the ACPI _DSM
  * Function 9 of the device, and cache the parent host bridge's flag for
  * ignoring reset delay upon Sx Resume (the flag is originally set in
  * acpi_pci_add_bus through _DSM Function 8).
@@ -1226,6 +1226,7 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 	u64 value_us;
 	int value;
 	union acpi_object *obj, *elements;
+	int i;
 
 	pdev->ignore_reset_delay_on_sx_resume =
 		bridge->ignore_reset_delay_on_sx_resume;
@@ -1237,21 +1238,26 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
 
 	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
 		elements = obj->package.elements;
-		if (elements[0].type == ACPI_TYPE_INTEGER) {
-			value_us = elements[0].integer.value;
-			value = (int)(value_us / 1000);
-			if (value_us % 1000 > 0)
-				value++;
-			if (value < PCI_RESET_DELAY)
-				pdev->d3cold_delay = value;
-		}
-		if (elements[3].type == ACPI_TYPE_INTEGER) {
-			value_us = elements[3].integer.value;
-			value = (int)(value_us / 1000);
-			if (value_us % 1000 > 0)
-				value++;
-			if (value < PCI_PM_D3HOT_DELAY)
-				pdev->d3_delay = value;
+		for (i = 0; i < 5; i++) {
+			if (elements[i].type == ACPI_TYPE_INTEGER) {
+				value_us = elements[i].integer.value;
+				value = (int)(value_us / 1000);
+				if (value_us % 1000 > 0)
+					value++;
+				/*
+				 * XXX This relies on the initial values in the
+				 * delay array being set using the PCI_*_DELAY
+				 * macros in drivers/pci/pci.h
+				 * Once the kernel has support for Readiness
+				 * Time Reporting Extended Capability, this
+				 * needs fixing to honor prioritization of
+				 * overrides. Also, a flag would need to be
+				 * set to disable the use of Readiness
+				 * Notifications at some point.
+				 */
+				if (value < pdev->delay[i])
+					pdev->delay[i] = value;
+			}
 		}
 	}
 	ACPI_FREE(obj);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index aaef00578487..ba54164652cc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -43,6 +43,15 @@ const char *pci_power_names[] = {
 };
 EXPORT_SYMBOL_GPL(pci_power_names);
 
+const char *pci_init_event_names[] = {
+	[PCI_INIT_EVENT_RESET] = "conventional reset",
+	[PCI_INIT_EVENT_DL_UP] = "DL Up",
+	[PCI_INIT_EVENT_FLR] = "FLR",
+	[PCI_INIT_EVENT_D3HOT_TO_D0] = "PM D3hot->D0",
+	[PCI_INIT_EVENT_VF_ENABLE] = "VF Enable",
+};
+EXPORT_SYMBOL_GPL(pci_init_event_names);
+
 int isa_dma_bridge_buggy;
 EXPORT_SYMBOL(isa_dma_bridge_buggy);
 
@@ -66,7 +75,7 @@ struct pci_pme_device {
 
 static void pci_dev_d3_sleep(struct pci_dev *dev)
 {
-	unsigned int delay = dev->d3_delay;
+	unsigned int delay = dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0];
 
 	if (delay < pci_pm_d3_delay)
 		delay = pci_pm_d3_delay;
@@ -2844,8 +2853,11 @@ void pci_pm_init(struct pci_dev *dev)
 
 	dev->pm_cap = pm;
 	dev->ignore_reset_delay_on_sx_resume = 0;
-	dev->d3_delay = PCI_PM_D3HOT_DELAY;
-	dev->d3cold_delay = PCI_RESET_DELAY;
+	dev->delay[PCI_INIT_EVENT_RESET] = PCI_RESET_DELAY;
+	dev->delay[PCI_INIT_EVENT_DL_UP] = PCI_DL_UP_DELAY;
+	dev->delay[PCI_INIT_EVENT_FLR] = PCI_FLR_DELAY;
+	dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] = PCI_PM_D3HOT_DELAY;
+	dev->delay[PCI_INIT_EVENT_VF_ENABLE] = PCI_VF_ENABLE_DELAY;
 	dev->bridge_d3 = pci_bridge_d3_possible(dev);
 	dev->d3cold_allowed = true;
 
@@ -4500,7 +4512,7 @@ int pcie_flr(struct pci_dev *dev)
 	if (dev->imm_ready)
 		return 0;
 
-	msleep(PCI_FLR_DELAY);
+	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
 	return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
 }
@@ -4539,7 +4551,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
 	if (dev->imm_ready)
 		return 0;
 
-	msleep(PCI_FLR_DELAY);
+	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
 	return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
 }
@@ -4556,7 +4568,9 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
  *
  * NOTE: This causes the caller to sleep for twice the device power transition
  * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
- * by default (i.e. unless the @dev's d3_delay field has a different value).
+ * by default (i.e. unless the @dev's delay[PCI_INIT_EVENT_D3HOT_TO_D0] field
+ * has a different value).
+ *
  * Moreover, only devices in D0 can be reset by this function.
  */
 static int pci_pm_reset(struct pci_dev *dev, int probe)
@@ -4666,12 +4680,14 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
 	const struct pci_dev *pdev;
 	int min_delay = 100;
 	int max_delay = 0;
+	int delay;
 
 	list_for_each_entry(pdev, &bus->devices, bus_list) {
-		if (pdev->d3cold_delay < min_delay)
-			min_delay = pdev->d3cold_delay;
-		if (pdev->d3cold_delay > max_delay)
-			max_delay = pdev->d3cold_delay;
+		delay = pdev->delay[PCI_INIT_EVENT_RESET];
+		if (delay < min_delay)
+			min_delay = delay;
+		if (delay > max_delay)
+			max_delay = delay;
 	}
 
 	return max(min_delay, max_delay);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 29f473ebf20f..12f22af0cbef 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1873,12 +1873,13 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);
 
 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
 {
-	if (dev->d3_delay >= delay)
+
+	if (dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] >= delay)
 		return;
 
-	dev->d3_delay = delay;
+	dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] = delay;
 	pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
-		 dev->d3_delay);
+		 dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0]);
 }
 
 static void quirk_radeon_pm(struct pci_dev *dev)
@@ -3310,7 +3311,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
  */
 static void quirk_remove_d3_delay(struct pci_dev *dev)
 {
-	dev->d3_delay = 0;
+	dev->delay[PCI_INIT_EVENT_D3HOT_TO_D0] = 0;
 }
 /* C600 Series devices do not need 10ms d3_delay */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 22a5b7164c32..16dbfff2092e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -268,6 +268,36 @@ enum pci_bus_speed {
 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 
+/*
+ * The first five constants correspond to delays specified in both:
+ * PCI Firmware Specification Rev. 3.2 (January 26, 2015),
+ * Section 4.6.9. "_DSM for Specifying Device Readiness Durations", and
+ * PCI Express Base Specification  Revision 5.0 Version 1.0 (May 22, 2019)
+ * Section 7.9.17 "Readiness Time Reporting Extended Capability"
+ *
+ * The code assumes these constants are in the same order as in the
+ * PCI Firmware Specification.
+ */
+enum pci_init_event {
+	PCI_INIT_EVENT_RESET		= 0, /* D3cold->D0, SBR */
+	PCI_INIT_EVENT_DL_UP		= 1,
+	PCI_INIT_EVENT_FLR		= 2,
+	PCI_INIT_EVENT_D3HOT_TO_D0	= 3,
+	PCI_INIT_EVENT_VF_ENABLE	= 4,
+	PCI_INIT_EVENT_COUNT  /* Keep this as last element */
+};
+
+/* Remember to update this when the list above changes! */
+extern const char *pci_init_event_names[];
+
+static inline const char *pci_init_event_name(enum pci_init_event event)
+{
+	if (event >= PCI_INIT_EVENT_COUNT)
+		return "<unknown>";
+	else
+		return pci_init_event_names[event];
+}
+
 struct pci_cap_saved_data {
 	u16		cap_nr;
 	bool		cap_extended;
@@ -356,8 +386,9 @@ struct pci_dev {
 						   bit manually */
 	unsigned int    ignore_reset_delay_on_sx_resume:1; /* Cached value from
 							      pci_host_bridge */
-	unsigned int	d3_delay;	/* D3->D0 transition time in ms */
-	unsigned int	d3cold_delay;	/* D3cold->D0 transition time in ms */
+	unsigned int    delay[PCI_INIT_EVENT_COUNT]; /* minimum waiting time
+							after various events
+							in ms */
 
 #ifdef CONFIG_PCIEASPM
 	struct pcie_link_state	*link_state;	/* ASPM link state */
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 09/17] PCI: Generalize pci_bus_max_d3cold_delay to pci_bus_max_delay
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (7 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 08/17] PCI: Add more delay overrides to struct pci_dev Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 10/17] PCI: Use correct delay in pci_bridge_wait_for_secondary_bus Stanislav Spassov
                   ` (7 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

This allows determining the maximum of any of the several delay values
stored in struct pci_dev.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index ba54164652cc..e4840dbf2d1c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4669,21 +4669,26 @@ bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
 }
 
 /*
- * Find maximum D3cold delay required by all the devices on the bus.  The
- * spec says 100 ms, but firmware can lower it and we allow drivers to
- * increase it as well.
+ * Find maximum delay required by all the devices on the bus after the
+ * given initialization event.
  *
  * Called with @pci_bus_sem locked for reading.
+ *
+ * XXX: It is not clear if this should descend down across bridges (if any)
  */
-static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
+static int pci_bus_max_delay(const struct pci_bus *bus,
+			     enum pci_init_event event, int default_delay)
 {
 	const struct pci_dev *pdev;
-	int min_delay = 100;
+	int min_delay = default_delay;
 	int max_delay = 0;
 	int delay;
 
+	if (event >= PCI_INIT_EVENT_COUNT)
+		return default_delay;
+
 	list_for_each_entry(pdev, &bus->devices, bus_list) {
-		delay = pdev->delay[PCI_INIT_EVENT_RESET];
+		delay = pdev->delay[event];
 		if (delay < min_delay)
 			min_delay = delay;
 		if (delay > max_delay)
@@ -4728,11 +4733,13 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, bool sx_resume)
 		return;
 	}
 
-	/* Take d3cold_delay requirements into account */
+	/* Take delay requirements into account */
 	if (sx_resume && dev->ignore_reset_delay_on_sx_resume)
 		delay = 0;
 	else
-		delay = pci_bus_max_d3cold_delay(dev->subordinate);
+		delay = pci_bus_max_delay(dev->subordinate,
+					  PCI_INIT_EVENT_RESET,
+					  PCI_RESET_DELAY);
 
 	if (!delay) {
 		up_read(&pci_bus_sem);
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 10/17] PCI: Use correct delay in pci_bridge_wait_for_secondary_bus
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (8 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 09/17] PCI: Generalize pci_bus_max_d3cold_delay to pci_bus_max_delay Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 11/17] PCI: Refactor pci_dev_wait to remove timeout parameter Stanislav Spassov
                   ` (6 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

PCI Express Base Specification r5.0 (May 22, 2019) details the rules
for device reset in Section 6.6.

For a Downstream Port that does not support Link speeds greater than
5.0 GT/s, the minimum waiting period before software is permitted to
send a Configuration Request after a Conventional Reset is 100ms
(PCI_RESET_DELAY).

For a Downstream Port that supports Link speeds greater than 5.0 GT/s
(such ports are required to be Data Link Layer Link Active Reporting
capable), the period is again 100ms but measured after the link has
become active (PCI_DL_UP_DELAY).

The delays for both cases above can be overridden independently, and
pci_bridge_wait_for_secondary_bus should use the appropriate one.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e4840dbf2d1c..7e08c5f38190 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4736,6 +4736,12 @@ void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, bool sx_resume)
 	/* Take delay requirements into account */
 	if (sx_resume && dev->ignore_reset_delay_on_sx_resume)
 		delay = 0;
+	else if (pcie_downstream_port(dev) &&
+		 pcie_get_speed_cap(dev) > PCIE_SPEED_5_0GT &&
+		 dev->link_active_reporting)
+		delay = pci_bus_max_delay(dev->subordinate,
+					  PCI_INIT_EVENT_DL_UP,
+					  PCI_DL_UP_DELAY);
 	else
 		delay = pci_bus_max_delay(dev->subordinate,
 					  PCI_INIT_EVENT_RESET,
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 11/17] PCI: Refactor pci_dev_wait to remove timeout parameter
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (9 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 10/17] PCI: Use correct delay in pci_bridge_wait_for_secondary_bus Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 12/17] PCI: Refactor pci_dev_wait to take pci_init_event Stanislav Spassov
                   ` (5 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Currently, all callers supply the same value, and in the future
pci_dev_wait itself could determine the appropriate timeout based on
values stored in struct pci_dev, and the reset type.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7e08c5f38190..9435e2b19f7b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1030,8 +1030,9 @@ void pci_wakeup_bus(struct pci_bus *bus)
 		pci_walk_bus(bus, pci_wakeup, NULL);
 }
 
-static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
+static int pci_dev_wait(struct pci_dev *dev, char *reset_type)
 {
+	int timeout = PCIE_RESET_READY_POLL_MS;
 	int delay = 1;
 	u32 id;
 
@@ -4514,7 +4515,7 @@ int pcie_flr(struct pci_dev *dev)
 
 	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
-	return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
+	return pci_dev_wait(dev, "FLR");
 }
 EXPORT_SYMBOL_GPL(pcie_flr);
 
@@ -4553,7 +4554,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
 
 	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
-	return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
+	return pci_dev_wait(dev, "AF_FLR");
 }
 
 /**
@@ -4600,7 +4601,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
 	pci_dev_d3_sleep(dev);
 
-	return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
+	return pci_dev_wait(dev, "PM D3hot->D0");
 }
 
 /**
@@ -4842,7 +4843,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
 {
 	pcibios_reset_secondary_bus(dev);
 
-	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
+	return pci_dev_wait(dev, "bus reset");
 }
 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
 
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 12/17] PCI: Refactor pci_dev_wait to take pci_init_event
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (10 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 11/17] PCI: Refactor pci_dev_wait to remove timeout parameter Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 13/17] PCI: Cache CRS Software Visibiliy in struct pci_dev Stanislav Spassov
                   ` (4 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Knowing what kind of event knocked the device out could be useful not
only for log output, but also to use different timeout/waiting behavior.

Note: we do lose some specificity in log output due to the aliasing of
FLR and AF_FLR, but it is doubtful the distinction is worthwhile.

Also, "bus reset" does not exactly match the more generic name for
PCI_INIT_EVENT_RESET, which could break programs that scrape kernel
output for overly specific patterns.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 9435e2b19f7b..5d62d4841d68 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1030,8 +1030,9 @@ void pci_wakeup_bus(struct pci_bus *bus)
 		pci_walk_bus(bus, pci_wakeup, NULL);
 }
 
-static int pci_dev_wait(struct pci_dev *dev, char *reset_type)
+static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
 {
+	const char *event_name = pci_init_event_name(event);
 	int timeout = PCIE_RESET_READY_POLL_MS;
 	int delay = 1;
 	u32 id;
@@ -1052,13 +1053,13 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type)
 	while (id == ~0) {
 		if (delay > timeout) {
 			pci_warn(dev, "not ready %dms after %s; giving up\n",
-				 delay - 1, reset_type);
+				 delay - 1, event_name);
 			return -ETIMEDOUT;
 		}
 
 		if (delay > 1000)
 			pci_info(dev, "not ready %dms after %s; waiting\n",
-				 delay - 1, reset_type);
+				 delay - 1, event_name);
 
 		msleep(delay);
 		delay *= 2;
@@ -1067,7 +1068,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type)
 
 	if (delay > 1000)
 		pci_info(dev, "ready %dms after %s\n", delay - 1,
-			 reset_type);
+			 event_name);
 
 	return 0;
 }
@@ -4515,7 +4516,7 @@ int pcie_flr(struct pci_dev *dev)
 
 	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
-	return pci_dev_wait(dev, "FLR");
+	return pci_dev_wait(dev, PCI_INIT_EVENT_FLR);
 }
 EXPORT_SYMBOL_GPL(pcie_flr);
 
@@ -4554,7 +4555,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
 
 	msleep(dev->delay[PCI_INIT_EVENT_FLR]);
 
-	return pci_dev_wait(dev, "AF_FLR");
+	return pci_dev_wait(dev, PCI_INIT_EVENT_FLR);
 }
 
 /**
@@ -4601,7 +4602,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
 	pci_dev_d3_sleep(dev);
 
-	return pci_dev_wait(dev, "PM D3hot->D0");
+	return pci_dev_wait(dev, PCI_INIT_EVENT_D3HOT_TO_D0);
 }
 
 /**
@@ -4843,7 +4844,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
 {
 	pcibios_reset_secondary_bus(dev);
 
-	return pci_dev_wait(dev, "bus reset");
+	return pci_dev_wait(dev, PCI_INIT_EVENT_RESET);
 }
 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
 
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 13/17] PCI: Cache CRS Software Visibiliy in struct pci_dev
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (11 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 12/17] PCI: Refactor pci_dev_wait to take pci_init_event Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 14/17] PCI: Introduce per-device reset_ready_poll override Stanislav Spassov
                   ` (3 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

Arguably, since CRS SV is a capability of Root Ports and determines
how Root Ports will handle incoming CRS Completions, it makes more
sense to store this flag in the struct pci bus that represents the
port's secondary bus, and to cache it in any buses further down the
hierarchy.

However, storing the flag in struct pci_dev allows individual devices
to be marked as not supporting CRS properly even when CRS SV is enabled
on their parent Root Port. This way, future code that relies on the new
flag will not be misled that it is safe to probe a device by relying on
CRS SV to not cause platform timeouts (See the note on CRS SV on p. 553
of PCI Express Base Specification r5.0 from May 22, 2019).

Note: Endpoints integrated into the Root Complex (RCiEP) may also be
capable of using CRS. In that case, the software visibility is
controlled using a Root Complex Register Block (RCRB). This is currently
not supported by the kernel. The code introduced here would simply not
set the newly introduced flag for RCiEP as for those bus->self is NULL.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/probe.c | 8 +++++++-
 include/linux/pci.h | 3 +++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 512cb4312ddd..eeff8a07f330 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1080,9 +1080,11 @@ static void pci_enable_crs(struct pci_dev *pdev)
 
 	/* Enable CRS Software Visibility if supported */
 	pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
-	if (root_cap & PCI_EXP_RTCAP_CRSVIS)
+	if (root_cap & PCI_EXP_RTCAP_CRSVIS) {
 		pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
 					 PCI_EXP_RTCTL_CRSSVE);
+		pdev->crssv_enabled = true;
+	}
 }
 
 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
@@ -2414,6 +2416,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
 	list_add_tail(&dev->bus_list, &bus->devices);
 	up_write(&pci_bus_sem);
 
+	/* Propagate CRS Software Visibility bit from the parent bridge */
+	if (bus->self)
+		dev->crssv_enabled = bus->self->crssv_enabled;
+
 	ret = pcibios_add_device(dev);
 	WARN_ON(ret < 0);
 
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 16dbfff2092e..1763e98625b9 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -386,6 +386,9 @@ struct pci_dev {
 						   bit manually */
 	unsigned int    ignore_reset_delay_on_sx_resume:1; /* Cached value from
 							      pci_host_bridge */
+	unsigned int	crssv_enabled:1;	/* Configuration Request Retry
+						   Status Software Visibility
+						   enabled on (parent) bridge */
 	unsigned int    delay[PCI_INIT_EVENT_COUNT]; /* minimum waiting time
 							after various events
 							in ms */
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 14/17] PCI: Introduce per-device reset_ready_poll override
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (12 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 13/17] PCI: Cache CRS Software Visibiliy in struct pci_dev Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 15/17] PCI: Refactor polling loop out of pci_dev_wait Stanislav Spassov
                   ` (2 subsequent siblings)
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

A broken device may never become responsive after reset, hence the need
for a timeout. However, waiting for too long can have unintended side
effects such as triggering hung task timeouts for processes waiting on
a lock held during the reset. Locks that are shared across multiple
devices, such as VFIO's per-bus reflck, are especially problematic,
because a single broken VF can cause hangs for processes working with
other VFs on the same bus.

To allow lowering the global default post-reset timeout, while still
accommodating devices that require more time, this patch introduces
a per-device override that can be configured via a quirk.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c   | 5 +----
 drivers/pci/pci.h   | 3 +++
 drivers/pci/probe.c | 2 ++
 include/linux/pci.h | 3 +++
 4 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 5d62d4841d68..e81fd3b53bd0 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -157,9 +157,6 @@ static int __init pcie_port_pm_setup(char *str)
 }
 __setup("pcie_port_pm=", pcie_port_pm_setup);
 
-/* Time to wait after a reset for device to become responsive */
-#define PCIE_RESET_READY_POLL_MS 60000
-
 /**
  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
  * @bus: pointer to PCI bus structure to search
@@ -1033,7 +1030,7 @@ void pci_wakeup_bus(struct pci_bus *bus)
 static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
 {
 	const char *event_name = pci_init_event_name(event);
-	int timeout = PCIE_RESET_READY_POLL_MS;
+	int timeout = dev->reset_ready_poll_ms;
 	int delay = 1;
 	u32 id;
 
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 9b5dd6ea2f52..d8043d4dbe2f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -113,6 +113,9 @@ int pci_bus_error_reset(struct pci_dev *dev);
 /* D0/D1->D2 and D2->D0 delay */
 #define PCI_PM_D2_DELAY		200
 
+/* Time to wait after a reset for device to become responsive */
+#define PCIE_RESET_READY_POLL_MS 60000
+
 /**
  * struct pci_platform_pm_ops - Firmware PM callbacks
  *
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index eeff8a07f330..50b7219406ed 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2168,6 +2168,8 @@ struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
 	if (!dev)
 		return NULL;
 
+	dev->reset_ready_poll_ms = PCIE_RESET_READY_POLL_MS;
+
 	INIT_LIST_HEAD(&dev->bus_list);
 	dev->dev.type = &pci_dev_type;
 	dev->bus = pci_bus_get(bus);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 1763e98625b9..978ede89741e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -392,6 +392,9 @@ struct pci_dev {
 	unsigned int    delay[PCI_INIT_EVENT_COUNT]; /* minimum waiting time
 							after various events
 							in ms */
+	unsigned int	reset_ready_poll_ms;	/* Timeout for polling after
+						   reset before the device is
+						   deemed broken. */
 
 #ifdef CONFIG_PCIEASPM
 	struct pcie_link_state	*link_state;	/* ASPM link state */
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 15/17] PCI: Refactor polling loop out of pci_dev_wait
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (13 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 14/17] PCI: Introduce per-device reset_ready_poll override Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 16/17] PCI: Add CRS handling to pci_dev_wait() Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 17/17] PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s Stanislav Spassov
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

This patch does not (intentionally) introduce any observable difference
in runtime behavior.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 71 +++++++++++++++++++++++++++++++++--------------
 1 file changed, 50 insertions(+), 21 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e81fd3b53bd0..f1ba931b0ead 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1027,27 +1027,28 @@ void pci_wakeup_bus(struct pci_bus *bus)
 		pci_walk_bus(bus, pci_wakeup, NULL);
 }
 
-static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
+/*
+ * Performs DWORD Configuration Reads at a specific offset until the value read
+ * (with mask applied) is not equal to bad_value.
+ */
+static inline int pci_dev_poll_until_not_equal(struct pci_dev *dev, int where,
+					       u32 mask, u32 bad_value,
+					       const char *event_name,
+					       int timeout, int *waited,
+					       u32 *final_value)
 {
-	const char *event_name = pci_init_event_name(event);
-	int timeout = dev->reset_ready_poll_ms;
 	int delay = 1;
-	u32 id;
+	u32 value;
 
-	/*
-	 * After reset, the device should not silently discard config
-	 * requests, but it may still indicate that it needs more time by
-	 * responding to them with CRS completions.  The Root Port will
-	 * generally synthesize ~0 data to complete the read (except when
-	 * CRS SV is enabled and the read was for the Vendor ID; in that
-	 * case it synthesizes 0x0001 data).
-	 *
-	 * Wait for the device to return a non-CRS completion.  Read the
-	 * Command register instead of Vendor ID so we don't have to
-	 * contend with the CRS SV value.
-	 */
-	pci_read_config_dword(dev, PCI_COMMAND, &id);
-	while (id == ~0) {
+	if (!event_name)
+		event_name = "<unknown event>";
+
+	if (waited)
+		delay = *waited + 1;
+
+	pci_read_config_dword(dev, where, &value);
+
+	while ((value & mask) == bad_value) {
 		if (delay > timeout) {
 			pci_warn(dev, "not ready %dms after %s; giving up\n",
 				 delay - 1, event_name);
@@ -1060,16 +1061,44 @@ static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
 
 		msleep(delay);
 		delay *= 2;
-		pci_read_config_dword(dev, PCI_COMMAND, &id);
+
+		pci_read_config_dword(dev, where, &value);
 	}
 
 	if (delay > 1000)
-		pci_info(dev, "ready %dms after %s\n", delay - 1,
-			 event_name);
+		pci_info(dev, "ready %dms after %s\n", delay - 1, event_name);
+
+	if (waited)
+		*waited = delay - 1;
+
+	if (final_value)
+		*final_value = value;
 
 	return 0;
 }
 
+static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
+{
+	const char *event_name = pci_init_event_name(event);
+	int timeout = dev->reset_ready_poll_ms;
+
+	/*
+	 * After reset, the device should not silently discard config
+	 * requests, but it may still indicate that it needs more time by
+	 * responding to them with CRS completions.  The Root Port will
+	 * generally synthesize ~0 data to complete the read (except when
+	 * CRS SV is enabled and the read was for the Vendor ID; in that
+	 * case it synthesizes 0x0001 data).
+	 *
+	 * Wait for the device to return a non-CRS completion.  Read the
+	 * Command register instead of Vendor ID so we don't have to
+	 * contend with the CRS SV value.
+	 */
+	return pci_dev_poll_until_not_equal(dev, PCI_COMMAND, ~0, ~0,
+					    event_name, timeout, NULL,
+					    NULL);
+}
+
 /**
  * pci_power_up - Put the given device into D0
  * @dev: PCI device to power up
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 16/17] PCI: Add CRS handling to pci_dev_wait()
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (14 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 15/17] PCI: Refactor polling loop out of pci_dev_wait Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  2020-03-02 18:44 ` [PATCH v2 17/17] PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s Stanislav Spassov
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

The PCI Express specification dictates minimal amounts of time that the
host needs to wait after triggering different kinds of resets before it
is allowed to attempt accessing the device. After this waiting period,
devices are required to be responsive to Configuration Space reads.
However, if a device needs more time to actually complete the reset
operation internally, it may respond to the read with a Completion
Request Retry Status (CRS), and keep doing so on subsequent reads
for as long as necessary. If the device is broken, it may even keep
responding with CRS indefinitely.

The specification also mandates that any Root Port that supports CRS
and has CRS Software Visibility (CRS SV) enabled will synthesize the
special value 0x0001 for the Vendor ID and set any other bits to 1
upon receiving a CRS Completion for a Configuration Read Request that
includes both bytes of the Vendor ID (offset 0).

IF CRS is supported by Root Port but CRS SV is not enabled, the request
is retried autonomosly by the Root Port. Platform-specific configuration
registers may exist to limit the number of or time taken by such retries.

If CRS is not supported, or a different register (not Vendor ID) is
polled, or the device is responding with CA/UR Completions (rather than
CRS), the behavior is platform-dependent, but generally the Root Port
synthesizes ~0 to complete the software read.

Previously, pci_dev_wait() avoided taking advantage of CRS. However,
on platforms where no limit/timeout can be configured as explained
above, a device responding with CRS for too long (e.g. because it is
stuck and cannot complete its reset) may trigger more severe error
conditions (e.g. TOR timeout, 3-strike CPU CATERR), because the Root
Port never reports back to the lower-level component requesting the
transaction.

This patch introduces special handling when CRS is available, and
otherwise falls back to the previous behavior of polling COMMAND.

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.c | 52 +++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f1ba931b0ead..1a504419e0de 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1081,18 +1081,54 @@ static int pci_dev_wait(struct pci_dev *dev, enum pci_init_event event)
 {
 	const char *event_name = pci_init_event_name(event);
 	int timeout = dev->reset_ready_poll_ms;
+	int waited = 0;
+	int rc = 0;
+
 
 	/*
 	 * After reset, the device should not silently discard config
 	 * requests, but it may still indicate that it needs more time by
-	 * responding to them with CRS completions.  The Root Port will
-	 * generally synthesize ~0 data to complete the read (except when
-	 * CRS SV is enabled and the read was for the Vendor ID; in that
-	 * case it synthesizes 0x0001 data).
-	 *
-	 * Wait for the device to return a non-CRS completion.  Read the
-	 * Command register instead of Vendor ID so we don't have to
-	 * contend with the CRS SV value.
+	 * responding to them with CRS completions. For such completions:
+	 * - If CRS SV is enabled on the Root Port, and the read request
+	 *   covers both bytes of the Vendor ID register, the Root Port
+	 *   will synthesize the value 0x0001 (and set any extra requested
+	 *   bytes to 0xff)
+	 * - If CRS SV is not enabled on the Root Port, the Root Port must
+	 *   re-issue the Configuration Request as a new Request.
+	 *   Depending on platform-specific Root Complex configurations,
+	 *   the Root Port may stop retrying after a set number of attempts,
+	 *   or a configured timeout is hit, or continue indefinitely
+	 *   (ultimately resulting in non-PCI-specific platform errors, such as
+	 *   a TOR timeout).
+	 */
+	if (dev->crssv_enabled) {
+		u32 id;
+
+		rc = pci_dev_poll_until_not_equal(dev, PCI_VENDOR_ID, 0xffff,
+						  0x0001, event_name, timeout,
+						  &waited, &id);
+		if (rc)
+			return rc;
+
+		/*
+		 * If Vendor/Device ID is valid, the device must be ready.
+		 * Note: SR-IOV VFs return ~0 for reads to Vendor/Device
+		 * ID and will not be recognized as ready by this check.
+		 */
+		if (id != 0x0000ffff && id != 0xffff0000 &&
+		    id != 0x00000000 && id != 0xffffffff)
+			return 0;
+	}
+
+	/*
+	 * Root Ports will generally indicate error scenarios (e.g.
+	 * internal timeouts, or received Completion with CA/UR) by
+	 * synthesizing an 'all bits set' value (~0).
+	 * In case CRS is not supported/enabled, as well as for SR-IOV VFs,
+	 * fall back to polling a different register that cannot validly
+	 * contain ~0. As of PCIe 5.0, bits 11-15 of COMMAND are still RsvdP
+	 * and must return 0 when read.
+	 * XXX: These bits might become meaningful in the future
 	 */
 	return pci_dev_poll_until_not_equal(dev, PCI_COMMAND, ~0, ~0,
 					    event_name, timeout, NULL,
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH v2 17/17] PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s
  2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
                   ` (15 preceding siblings ...)
  2020-03-02 18:44 ` [PATCH v2 16/17] PCI: Add CRS handling to pci_dev_wait() Stanislav Spassov
@ 2020-03-02 18:44 ` Stanislav Spassov
  16 siblings, 0 replies; 22+ messages in thread
From: Stanislav Spassov @ 2020-03-02 18:44 UTC (permalink / raw)
  To: linux-pci
  Cc: Stanislav Spassov, Bjorn Helgaas, Thomas Gleixner, Andrew Morton,
	Jan H . Schönherr, Jonathan Corbet, Ashok Raj,
	Alex Williamson, Sinan Kaya, Rajat Jain

From: Stanislav Spassov <stanspas@amazon.de>

PCI Express Base specification r5.0 (May 22, 2019), sec 6.6.1 mentions
on more than one occasion that the appropriate waiting time before
deeming a device broken if it is not able to return Successful
Completion for valid Configuration Requests is 1 second after a
Conventional Reset (which should be the lengthiest of resets).

For devices that take longer than 1s to complete initialization, quirks
can override the waiting time via the reset_ready_poll_ms field in
struct pci_dev.

Note: This timeout is used in pci_dev_wait for the polling that happens
after we have already waited for the required post-reset times mandated
by the spec. All devices are expected to be responsive to Configuration
Requests at that point. "Completing initialization" here means that the
device is not only responsive, but actually returns Successful
Completions rather than CRS Completions (or any other error).

Signed-off-by: Stanislav Spassov <stanspas@amazon.de>
---
 drivers/pci/pci.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d8043d4dbe2f..1c6722b5c3ee 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -113,8 +113,11 @@ int pci_bus_error_reset(struct pci_dev *dev);
 /* D0/D1->D2 and D2->D0 delay */
 #define PCI_PM_D2_DELAY		200
 
-/* Time to wait after a reset for device to become responsive */
-#define PCIE_RESET_READY_POLL_MS 60000
+/*
+ * Time to wait (in addition to the delays above) for a device to start
+ * returning Successful Completions before OS can deem it broken
+ */
+#define PCIE_RESET_READY_POLL_MS 1000
 
 /**
  * struct pci_platform_pm_ops - Firmware PM callbacks
-- 
2.25.1




Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879




^ permalink raw reply related	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 07/17] PCI: Clean up and document PM/reset delays
  2020-03-02 18:44 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays Stanislav Spassov
@ 2020-03-03  1:51   ` kbuild test robot
  2020-03-03  2:54   ` kbuild test robot
  1 sibling, 0 replies; 22+ messages in thread
From: kbuild test robot @ 2020-03-03  1:51 UTC (permalink / raw)
  To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List

[-- Attachment #1: Type: text/plain, Size: 4509 bytes --]

Hi Stanislav,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]

url:    https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base:    bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/pci/controller/pci-mvebu.c: In function 'mvebu_pcie_powerup':
>> drivers/pci/controller/pci-mvebu.c:930:22: error: 'PCI_PM_D3COLD_WAIT' undeclared (first use in this function); did you mean 'PCI_PM_D3HOT_DELAY'?
      u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
                         ^~~~~~~~~~~~~~~~~~
                         PCI_PM_D3HOT_DELAY
   drivers/pci/controller/pci-mvebu.c:930:22: note: each undeclared identifier is reported only once for each function it appears in

vim +930 drivers/pci/controller/pci-mvebu.c

49cb1f718360f8 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  915  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  916  /*
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  917   * Power up a PCIe port.  PCIe requires the refclk to be stable for 100µs
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  918   * prior to releasing PERST.  See table 2-4 in section 2.6.2 AC Specifications
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  919   * of the PCI Express Card Electromechanical Specification, 1.1.
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  920   */
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  921  static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  922  {
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  923  	int ret;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  924  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  925  	ret = clk_prepare_enable(port->clk);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  926  	if (ret < 0)
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  927  		return ret;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  928  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  929  	if (port->reset_gpio) {
8ed81ec82a8c57 drivers/pci/host/pci-mvebu.c Lucas Stach  2017-02-02 @930  		u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  931  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  932  		of_property_read_u32(port->dn, "reset-delay-us",
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  933  				     &reset_udelay);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  934  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  935  		udelay(100);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  936  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  937  		gpiod_set_value_cansleep(port->reset_gpio, 0);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  938  		msleep(reset_udelay / 1000);
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  939  	}
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  940  
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  941  	return 0;
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  942  }
d609a8d8e88a42 drivers/pci/host/pci-mvebu.c Russell King 2015-10-03  943  

:::::: The code at line 930 was first introduced by commit
:::::: 8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256 PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms

:::::: TO: Lucas Stach <l.stach@pengutronix.de>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 34127 bytes --]

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 07/17] PCI: Clean up and document PM/reset delays
  2020-03-02 18:44 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays Stanislav Spassov
  2020-03-03  1:51   ` kbuild test robot
@ 2020-03-03  2:54   ` kbuild test robot
  1 sibling, 0 replies; 22+ messages in thread
From: kbuild test robot @ 2020-03-03  2:54 UTC (permalink / raw)
  To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List

[-- Attachment #1: Type: text/plain, Size: 15093 bytes --]

Hi Stanislav,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]

url:    https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base:    bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.5.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.5.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/pci/controller/pci-aardvark.c: In function 'advk_pcie_setup_hw':
>> drivers/pci/controller/pci-aardvark.c:347:9: error: 'PCI_PM_D3COLD_WAIT' undeclared (first use in this function); did you mean 'PCI_PM_D3HOT_DELAY'?
     msleep(PCI_PM_D3COLD_WAIT);
            ^~~~~~~~~~~~~~~~~~
            PCI_PM_D3HOT_DELAY
   drivers/pci/controller/pci-aardvark.c:347:9: note: each undeclared identifier is reported only once for each function it appears in

vim +347 drivers/pci/controller/pci-aardvark.c

364b3f1ff8f096 drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  255  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  256  static void advk_pcie_setup_hw(struct advk_pcie *pcie)
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  257  {
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  258  	u32 reg;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  259  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  260  	/* Set to Direct mode */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  261  	reg = advk_readl(pcie, CTRL_CONFIG_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  262  	reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  263  	reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  264  	advk_writel(pcie, reg, CTRL_CONFIG_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  265  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  266  	/* Set PCI global control register to RC mode */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  267  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  268  	reg |= (IS_RC_MSK << IS_RC_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  269  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  270  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  271  	/* Set Advanced Error Capabilities and Control PF0 register */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  272  	reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  273  		PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  274  		PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  275  		PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  276  	advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  277  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  278  	/* Set PCIe Device Control and Status 1 PF0 register */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  279  	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  280  		(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  281  		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
fc31c4e347c9da drivers/pci/host/pci-aardvark.c       Evan Wang        2018-04-06  282  		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
fc31c4e347c9da drivers/pci/host/pci-aardvark.c       Evan Wang        2018-04-06  283  		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  284  	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  285  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  286  	/* Program PCIe Control 2 to disable strict ordering */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  287  	reg = PCIE_CORE_CTRL2_RESERVED |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  288  		PCIE_CORE_CTRL2_TD_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  289  	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  290  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  291  	/* Set GEN2 */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  292  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  293  	reg &= ~PCIE_GEN_SEL_MSK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  294  	reg |= SPEED_GEN_2;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  295  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  296  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  297  	/* Set lane X1 */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  298  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  299  	reg &= ~LANE_CNT_MSK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  300  	reg |= LANE_COUNT_1;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  301  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  302  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  303  	/* Enable link training */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  304  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  305  	reg |= LINK_TRAINING_EN;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  306  	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  307  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  308  	/* Enable MSI */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  309  	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  310  	reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  311  	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  312  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  313  	/* Clear all interrupts */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  314  	advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  315  	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  316  	advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  317  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  318  	/* Disable All ISR0/1 Sources */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  319  	reg = PCIE_ISR0_ALL_MASK;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  320  	reg &= ~PCIE_ISR0_MSI_INT_PENDING;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  321  	advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  322  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  323  	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  324  
f6b6aefee70aa5 drivers/pci/controller/pci-aardvark.c Bjorn Helgaas    2019-05-30  325  	/* Unmask all MSIs */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  326  	advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  327  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  328  	/* Enable summary interrupt for GIC SPI source */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  329  	reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  330  	advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  331  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  332  	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  333  	reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  334  	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  335  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  336  	/* Bypass the address window mapping for PIO */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  337  	reg = advk_readl(pcie, PIO_CTRL);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  338  	reg |= PIO_CTRL_ADDR_WIN_DISABLE;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  339  	advk_writel(pcie, reg, PIO_CTRL);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  340  
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  341  	/*
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  342  	 * PERST# signal could have been asserted by pinctrl subsystem before
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  343  	 * probe() callback has been called, making the endpoint going into
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  344  	 * fundamental reset. As required by PCI Express spec a delay for at
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  345  	 * least 100ms after such a reset before link training is needed.
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  346  	 */
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22 @347  	msleep(PCI_PM_D3COLD_WAIT);
f4c7d053d7f77c drivers/pci/controller/pci-aardvark.c Remi Pommarel    2019-05-22  348  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  349  	/* Start link training */
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  350  	reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  351  	reg |= PCIE_CORE_LINK_TRAINING;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  352  	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  353  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  354  	advk_pcie_wait_for_link(pcie);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  355  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  356  	reg = PCIE_CORE_LINK_L0S_ENTRY |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  357  		(1 << PCIE_CORE_LINK_WIDTH_SHIFT);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  358  	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  359  
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  360  	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  361  	reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  362  		PCIE_CORE_CMD_IO_ACCESS_EN |
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  363  		PCIE_CORE_CMD_MEM_IO_REQ_EN;
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  364  	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  365  }
8c39d710363c14 drivers/pci/host/pci-aardvark.c       Thomas Petazzoni 2016-06-30  366  

:::::: The code at line 347 was first introduced by commit
:::::: f4c7d053d7f77cd5c1a1ba7c7ce085ddba13d1d7 PCI: aardvark: Wait for endpoint to be ready before training link

:::::: TO: Remi Pommarel <repk@triplefau.lt>
:::::: CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
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^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay
  2020-03-02 18:44 ` [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay Stanislav Spassov
@ 2020-03-03  4:19   ` kbuild test robot
  2020-03-03  5:54   ` kbuild test robot
  1 sibling, 0 replies; 22+ messages in thread
From: kbuild test robot @ 2020-03-03  4:19 UTC (permalink / raw)
  To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List

[-- Attachment #1: Type: text/plain, Size: 1085 bytes --]

Hi Stanislav,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]

url:    https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base:    bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: i386-randconfig-h002-20200302 (attached as .config)
compiler: gcc-7 (Debian 7.5.0-5) 7.5.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   ld: drivers/pci/pci-acpi.o: in function `pci_acpi_setup':
>> pci-acpi.c:(.text+0xb9a): undefined reference to `__udivdi3'
>> ld: pci-acpi.c:(.text+0xbb5): undefined reference to `__umoddi3'
   ld: pci-acpi.c:(.text+0xc39): undefined reference to `__udivdi3'
   ld: pci-acpi.c:(.text+0xc54): undefined reference to `__umoddi3'

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 34309 bytes --]

^ permalink raw reply	[flat|nested] 22+ messages in thread

* Re: [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay
  2020-03-02 18:44 ` [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay Stanislav Spassov
  2020-03-03  4:19   ` kbuild test robot
@ 2020-03-03  5:54   ` kbuild test robot
  1 sibling, 0 replies; 22+ messages in thread
From: kbuild test robot @ 2020-03-03  5:54 UTC (permalink / raw)
  To: Stanislav Spassov; +Cc: kbuild-all, linux-pci, Linux Memory Management List

[-- Attachment #1: Type: text/plain, Size: 5067 bytes --]

Hi Stanislav,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9]

url:    https://github.com/0day-ci/linux/commits/Stanislav-Spassov/Improve-PCI-device-post-reset-readiness-polling/20200303-043307
base:    bb6d3fb354c5ee8d6bde2d576eb7220ea09862b9
config: i386-randconfig-d001-20200302 (attached as .config)
compiler: gcc-7 (Debian 7.5.0-5) 7.5.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   ld: drivers/pci/pci-acpi.o: in function `pci_acpi_optimize_delay':
>> drivers/pci/pci-acpi.c:1242: undefined reference to `__udivdi3'
>> ld: drivers/pci/pci-acpi.c:1243: undefined reference to `__umoddi3'
   ld: drivers/pci/pci-acpi.c:1250: undefined reference to `__udivdi3'
   ld: drivers/pci/pci-acpi.c:1251: undefined reference to `__umoddi3'

vim +1242 drivers/pci/pci-acpi.c

  1178	
  1179	/**
  1180	 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
  1181	 * @pdev: the PCI device whose delay is to be updated
  1182	 * @handle: ACPI handle of this device
  1183	 *
  1184	 * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
  1185	 * Function 9 of the device, and cache the parent host bridge's flag for
  1186	 * ignoring reset delay upon Sx Resume (the flag is originally set in
  1187	 * acpi_pci_add_bus through _DSM Function 8).
  1188	 *
  1189	 * Function 9, "Device Readiness Durations," applies only to the object
  1190	 * where it is located.  It returns delay durations required after various
  1191	 * events if the device requires less time than the spec requires.
  1192	 * Values provided by this function can only be used to lower (reduce) the
  1193	 * latency required by specification or values discovered from device.
  1194	 *
  1195	 * This _DSM function is defined by the PCI Firmware Specification Rev 3.2
  1196	 * (January 26, 2015), after originally introduced by a draft ECN of
  1197	 * January 28, 2014, titled "ACPI additions for FW latency optimizations."
  1198	 *
  1199	 * XXX The PCI Firmware Specification contradicts itself by stating, in addition
  1200	 * to the above "can only be used to lower (reduce)", that also:
  1201	 * Values must be interpreted as overriding any Configuration Ready indicator
  1202	 * from hardware, whether increasing or decreasing required delays. This
  1203	 * includes ignoring FRS and DRS notifications where overridden by this
  1204	 * _DSM function, as well as ignoring values specified in the Readiness Time
  1205	 * Reporting Extended Capability, if present.
  1206	 * Meanwhile, the PCI Express Base Specification Revision 5.0 Version 1.0
  1207	 * (22 May 2019) states in section 7.9.17 Readiness Time Reporting Extended
  1208	 * Capability:
  1209	 * Software is permitted to issue requests upon the earliest of:
  1210	 * - Receiving a Readiness Notification messages
  1211	 * - Waiting the appropriate time as per relevant specifications
  1212	 * - Waiting the time indicated in the associated field of this capability
  1213	 * - Waiting the time defined by system software or firmware
  1214	 * The kernel does not yet support Readiness Notifications, and does not yet
  1215	 * use a Readiness Time Reporting capability if present, so we do not need to
  1216	 * worry about the prioritization for now.
  1217	 */
  1218	static void pci_acpi_optimize_delay(struct pci_dev *pdev,
  1219					    acpi_handle handle)
  1220	{
  1221		struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
  1222		/*
  1223		 * _DSM 9 provides values in microseconds, but the kernel uses msleep()
  1224		 * when waiting, so the code below rounds up when setting value in ms
  1225		 */
  1226		u64 value_us;
  1227		int value;
  1228		union acpi_object *obj, *elements;
  1229	
  1230		pdev->ignore_reset_delay_on_sx_resume =
  1231			bridge->ignore_reset_delay_on_sx_resume;
  1232	
  1233		obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 3,
  1234					FUNCTION_DELAY_DSM, NULL);
  1235		if (!obj)
  1236			return;
  1237	
  1238		if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
  1239			elements = obj->package.elements;
  1240			if (elements[0].type == ACPI_TYPE_INTEGER) {
  1241				value_us = elements[0].integer.value;
> 1242				value = (int)(value_us / 1000);
> 1243				if (value_us % 1000 > 0)
  1244					value++;
  1245				if (value < PCI_PM_D3COLD_WAIT)
  1246					pdev->d3cold_delay = value;
  1247			}
  1248			if (elements[3].type == ACPI_TYPE_INTEGER) {
  1249				value_us = elements[3].integer.value;
  1250				value = (int)(value_us / 1000);
  1251				if (value_us % 1000 > 0)
  1252					value++;
  1253				if (value < PCI_PM_D3_WAIT)
  1254					pdev->d3_delay = value;
  1255			}
  1256		}
  1257		ACPI_FREE(obj);
  1258	}
  1259	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
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^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2020-03-03  5:55 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-02 18:44 [PATCH v2 00/17] Improve PCI device post-reset readiness polling Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 01/17] PCI: Fall back to slot/bus reset if softer methods timeout Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 02/17] PCI: Remove unused PCI_PM_BUS_WAIT Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 03/17] PCI: Use pci_bridge_wait_for_secondary_bus after SBR Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 04/17] PCI: Do not override delay for D0->D3hot transition Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 05/17] PCI: Fix handling of _DSM 8 (avoiding reset delays) Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 06/17] PCI: Fix us->ms conversion in pci_acpi_optimize_delay Stanislav Spassov
2020-03-03  4:19   ` kbuild test robot
2020-03-03  5:54   ` kbuild test robot
2020-03-02 18:44 ` [PATCH v2 07/17] PCI: Clean up and document PM/reset delays Stanislav Spassov
2020-03-03  1:51   ` kbuild test robot
2020-03-03  2:54   ` kbuild test robot
2020-03-02 18:44 ` [PATCH v2 08/17] PCI: Add more delay overrides to struct pci_dev Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 09/17] PCI: Generalize pci_bus_max_d3cold_delay to pci_bus_max_delay Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 10/17] PCI: Use correct delay in pci_bridge_wait_for_secondary_bus Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 11/17] PCI: Refactor pci_dev_wait to remove timeout parameter Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 12/17] PCI: Refactor pci_dev_wait to take pci_init_event Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 13/17] PCI: Cache CRS Software Visibiliy in struct pci_dev Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 14/17] PCI: Introduce per-device reset_ready_poll override Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 15/17] PCI: Refactor polling loop out of pci_dev_wait Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 16/17] PCI: Add CRS handling to pci_dev_wait() Stanislav Spassov
2020-03-02 18:44 ` [PATCH v2 17/17] PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s Stanislav Spassov

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