From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8176C3F2D1 for ; Tue, 3 Mar 2020 18:11:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0FD2208C3 for ; Tue, 3 Mar 2020 18:11:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="HlJ1JHUG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732167AbgCCSLK (ORCPT ); Tue, 3 Mar 2020 13:11:10 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:5860 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732578AbgCCSLA (ORCPT ); Tue, 3 Mar 2020 13:11:00 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 03 Mar 2020 10:09:35 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 03 Mar 2020 10:10:59 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 03 Mar 2020 10:10:59 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 3 Mar 2020 18:10:59 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 3 Mar 2020 18:10:59 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 03 Mar 2020 10:10:58 -0800 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , Subject: [PATCH V5 0/5] Add support for PCIe endpoint mode in Tegra194 Date: Tue, 3 Mar 2020 23:40:47 +0530 Message-ID: <20200303181052.16134-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583258975; bh=5Fi5EdkTRLJSkgJn2+bJTvH1pwqa1HK8kIxRNGDAs7U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=HlJ1JHUG6LFN1V+IpdBcRhoueciZF5g8eBpo/lAXJ3yTbaIKSvjSGNDFe61KL53ig l+E18TCd35Af6hlGeWtlaX/qkC7jixISIa/NwPkoqYspC1H33u8wRMrztl16T4vRUI tVwe9oeajeFSAid4oxspLzKpsEq+VnWYCI5/dnnvKnK8PxXAe+G0dmH1ZkxOYZehvK x/AUHL0SH7y4PLhGOZHgDf8nZpBp4YbWruLIemIyXHTSEI+wRm8MMnVVhEkzH2yX+Y vL1hjuEcgQTghOp9KKRsXA2Klw/Etaptf+gzG0P6QnbnvPz8SuZqbqLDxQ+l6nSVTc FNlInQo8OLbgg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra194 has three (C0, C4 & C5) dual mode PCIe controllers that can operate either in root port mode or in end point mode but only in one mode at a time. Platform P2972-0000 supports enabling endpoint mode for C5 controller. This patch series adds support for PCIe endpoint mode in both the driver as well as in DT. This patch series depends on the changes made for Synopsys DesignWare endpoint mode subsystem that are recently accepted. @ https://patchwork.kernel.org/project/linux-pci/list/?series=202211 which in turn depends on the patch made by Kishon @ https://patchwork.kernel.org/patch/10975123/ which is also under review. V5: * Rebased patch-2 on top of Lorenzo's pci/endpoint branch * Removed unwanted header files inclusion in patch-5 V4: * Started using threaded irqs instead of kthreads V3: * Re-ordered patches in the series to make the driver change as the last patch * Took care of Thierry's review comments V2: * Addressed Thierry & Bjorn's review comments * Added EP mode specific binding documentation to already existing binding documentation file * Removed patch that enables GPIO controller nodes explicitly as they are enabled already Vidya Sagar (5): soc/tegra: bpmp: Update ABI header dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194 arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform PCI: tegra: Add support for PCIe endpoint mode in Tegra194 .../bindings/pci/nvidia,tegra194-pcie.txt | 125 +++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 18 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 99 +++ drivers/pci/controller/dwc/Kconfig | 30 +- drivers/pci/controller/dwc/pcie-tegra194.c | 679 +++++++++++++++++- include/soc/tegra/bpmp-abi.h | 10 +- 6 files changed, 916 insertions(+), 45 deletions(-) -- 2.17.1