From: Bjorn Helgaas <helgaas@kernel.org>
To: Yicong Yang <yangyicong@hisilicon.com>
Cc: linux-pci@vger.kernel.org, rajatja@google.com,
f.fangjian@huawei.com, huangdaode@huawei.com
Subject: Re: [PATCH] PCI/PM: Fix wrong field set when config L1SS
Date: Thu, 12 Mar 2020 14:42:02 -0500 [thread overview]
Message-ID: <20200312194202.GA162085@google.com> (raw)
In-Reply-To: <1584012191-34129-1-git-send-email-yangyicong@hisilicon.com>
On Thu, Mar 12, 2020 at 07:23:11PM +0800, Yicong Yang wrote:
> We enable proper L1 substates in the end of pcie_config_aspm_l1ss(). It's
> PCI_L1SS_CTL1_L1SS_MASK field should we set in PCI_L1SS_CTL1 register
> rather than PCI_L1SS_CAP_L1_PM_SS.
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Would you mind digging up the commit that broke this and including it
in the log message? Then we can see if this fix should go to stable
and, if so, how far back.
> ---
> drivers/pci/pcie/aspm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 0dcd443..c2596e7 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
>
> /* Enable what we need to enable */
> pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
> - PCI_L1SS_CAP_L1_PM_SS, val);
> + PCI_L1SS_CTL1_L1SS_MASK, val);
> pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
> - PCI_L1SS_CAP_L1_PM_SS, val);
> + PCI_L1SS_CTL1_L1SS_MASK, val);
> }
>
> static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
> --
> 2.8.1
>
prev parent reply other threads:[~2020-03-12 19:42 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 11:23 [PATCH] PCI/PM: Fix wrong field set when config L1SS Yicong Yang
2020-03-12 19:42 ` Bjorn Helgaas [this message]
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