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From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: Zhiqiang.Hou@nxp.com, Minghuan.Lian@nxp.com, mingkai.hu@nxp.com,
	bhelgaas@google.com, robh+dt@kernel.org, shawnguo@kernel.org,
	leoyang.li@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com,
	roy.zang@nxp.com, amurray@thegoodpenguin.co.uk,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
	andrew.murray@arm.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCH v6 02/11] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
Date: Sat, 14 Mar 2020 11:30:29 +0800
Message-ID: <20200314033038.24844-3-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20200314033038.24844-1-xiaowei.bao@nxp.com>

Add the doorbell mode of MSI-X in DWC EP driver.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
 - Remove the macro of no used.
v3:
 - No change.
v4:
 - Modify the commit message.
v5:
 - No change.
v6:
 - No change.

 drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h    | 12 ++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 58d8556..44ece33 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -449,6 +449,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+				       u16 interrupt_num)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	u32 msg_data;
+
+	msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
+		   (interrupt_num - 1);
+
+	dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
+
+	return 0;
+}
+
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 			      u16 interrupt_num)
 {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00d2d31..cb32afa 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -97,6 +97,9 @@
 #define PCIE_MISC_CONTROL_1_OFF		0x8BC
 #define PCIE_DBI_RO_WR_EN		BIT(0)
 
+#define PCIE_MSIX_DOORBELL		0x948
+#define PCIE_MSIX_DOORBELL_PF_SHIFT	24
+
 #define PCIE_PL_CHK_REG_CONTROL_STATUS			0xB20
 #define PCIE_PL_CHK_REG_CHK_REG_START			BIT(0)
 #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS		BIT(1)
@@ -431,6 +434,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 			     u8 interrupt_num);
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 			     u16 interrupt_num);
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+				       u16 interrupt_num);
 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 #else
 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
@@ -463,6 +468,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
+						     u8 func_no,
+						     u16 interrupt_num)
+{
+	return 0;
+}
+
 static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 {
 }
-- 
2.9.5


  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-14  3:30 [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 01/11] PCI: designware-ep: Add multiple PFs support for DWC Xiaowei Bao
2020-05-20 20:32   ` Rob Herring
2020-03-14  3:30 ` Xiaowei Bao [this message]
2020-03-14  3:30 ` [PATCH v6 03/11] PCI: designware-ep: Move the function of getting MSI capability forward Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding Xiaowei Bao
2020-05-20 20:45   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 05/11] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 06/11] PCI: layerscape: Fix some format issue of the code Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 07/11] PCI: layerscape: Modify the way of getting capability with different PEX Xiaowei Bao
2020-05-20 20:45   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 08/11] PCI: layerscape: Modify the MSIX to the doorbell mode Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 09/11] PCI: layerscape: Add EP mode support for ls1088a and ls2088a Xiaowei Bao
2020-05-20 20:50   ` Rob Herring
2020-03-14  3:30 ` [PATCH v6 10/11] arm64: dts: layerscape: Add PCIe EP node for ls1088a Xiaowei Bao
2020-03-14  3:30 ` [PATCH v6 11/11] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Xiaowei Bao
2020-07-06 10:46 ` [PATCH v6 00/11] Add the multiple PF support for DWC and Layerscape Lorenzo Pieralisi
2020-07-07  2:10   ` Z.q. Hou

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